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Message-ID: <2e781a85-30bc-4765-876c-28a0c2fe5cdf@linaro.org>
Date:   Fri, 8 Dec 2023 19:01:13 +0100
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Conor Dooley <conor@...nel.org>, palmer@...belt.com
Cc:     Conor Dooley <conor.dooley@...rochip.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1] dt-bindings: riscv: permit numbers in "riscv,isa"

On 08/12/2023 17:06, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@...rochip.com>
> 
> There are some extensions that contain numbers, such as Zve32f, which
> are enabled by the "max" cpu type in QEMU.
> 
> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>

That regex exceeded my capabilities long time ago, so just formality, FWIW:

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>

Best regards,
Krzysztof

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