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Message-ID: <b3690246eb1e48428238ceb26b046297@EXMBX066.cuchost.com>
Date: Mon, 11 Dec 2023 09:38:03 +0000
From: JeeHeng Sia <jeeheng.sia@...rfivetech.com>
To: Conor Dooley <conor.dooley@...rochip.com>
CC: Shengyu Qu <wiagn233@...look.com>,
"kernel@...il.dk" <kernel@...il.dk>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
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<krzysztof.kozlowski+dt@...aro.org>,
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Leyfoon Tan <leyfoon.tan@...rfivetech.com>
Subject: RE: [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100
device tree
> -----Original Message-----
> From: Conor Dooley <conor.dooley@...rochip.com>
> Sent: Monday, December 11, 2023 3:59 PM
> To: JeeHeng Sia <jeeheng.sia@...rfivetech.com>
> Cc: Shengyu Qu <wiagn233@...look.com>; kernel@...il.dk; robh+dt@...nel.org; krzysztof.kozlowski+dt@...aro.org;
> krzk@...nel.org; conor+dt@...nel.org; paul.walmsley@...ive.com; palmer@...belt.com; aou@...s.berkeley.edu;
> daniel.lezcano@...aro.org; tglx@...utronix.de; conor@...nel.org; anup@...infault.org; gregkh@...uxfoundation.org;
> jirislaby@...nel.org; michal.simek@....com; Michael Zhu <michael.zhu@...rfivetech.com>; drew@...gleboard.org;
> devicetree@...r.kernel.org; linux-riscv@...ts.infradead.org; linux-kernel@...r.kernel.org; Leyfoon Tan
> <leyfoon.tan@...rfivetech.com>
> Subject: Re: [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree
>
> On Mon, Dec 11, 2023 at 01:38:06AM +0000, JeeHeng Sia wrote:
> >
> > > From: Shengyu Qu <wiagn233@...look.com>
> > > Sent: Friday, December 8, 2023 8:09 PM
>
> > > Does the dubhe-80 cores actually support vector? Or vector support
> > >
> > > doesn't exist on actual silicon?
>
> > We don't have a use case for vector application in JH8100
>
> I am sorry, but I am not clear on what this means. Do the CPUs on
> the JH8100 support vector or not?
The JH8100 CPU does not support vector operation.
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