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Message-ID: <0164c37a-872f-43d0-9b3f-f351a7fda31c@amd.com>
Date:   Wed, 13 Dec 2023 16:45:08 +0100
From:   Michal Simek <michal.simek@....com>
To:     conor@...nel.org, linux-kernel@...r.kernel.org, monstr@...str.eu,
        michal.simek@...inx.com, git@...inx.com, robh@...nel.org
Cc:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v4 2/2] dt-bindings: soc: Add new board description for
 MicroBlaze V



On 11/23/23 08:02, Michal Simek wrote:
> MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
> It is hardware compatible with classic MicroBlaze processor. Processor can
> be used with standard AMD/Xilinx IPs including interrupt controller and
> timer.
> 
> Signed-off-by: Michal Simek <michal.simek@....com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> ---
> 
> Changes in v4:
> - Fix indentation reported by bot
> 
> Changes in v3:
> - Add Krzysztof's ACK
> 
> Changes in v2:
> - Put MicroBlaze V description to xilinx.yaml
> - Add qemu target platform as platform used for testing.
> 
>   Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml | 5 +++++
>   1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
> index 95758deca325..d4c0fe1fe435 100644
> --- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
> +++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
> @@ -132,6 +132,11 @@ properties:
>             - const: xlnx,zynqmp-smk-k26
>             - const: xlnx,zynqmp
>   
> +      - description: AMD MicroBlaze V (QEMU)
> +        items:
> +          - const: qemu,mbv
> +          - const: amd,mbv
> +
>   additionalProperties: true
>   
>   ...

Applied.
M

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