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Message-ID: <CAMuHMdXwRZRvLPh3JBShQy4hRHq=2fQJmcYjTyQhKZmtBPaOuw@mail.gmail.com>
Date: Wed, 13 Dec 2023 16:51:30 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Conor Dooley <conor@...nel.org>
Cc: linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Emil Renner Berthing <emil.renner.berthing@...onical.com>,
Conor Dooley <conor.dooley@...rochip.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Emil Renner Berthing <kernel@...il.dk>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Cristian Ciocaltea <cristian.ciocaltea@...labora.com>
Subject: Re: (subset) [PATCH v2 0/8] Add JH7100 errata and update device tree
Hi Conor,
On Wed, Dec 13, 2023 at 4:43 PM Conor Dooley <conor@...nel.org> wrote:
> From: Conor Dooley <conor.dooley@...rochip.com>
>
> On Thu, 30 Nov 2023 16:19:24 +0100, Emil Renner Berthing wrote:
> > Now that the driver for the SiFive cache controller supports manual
> > flushing as non-standard cache operations[1] we can add an errata option
> > for the StarFive JH7100 SoC and update the device tree with the cache
> > controller, dedicated DMA pool and add MMC nodes for the SD-card and
> > wifi.
> >
> > This series needs the following commit in [1] to work properly:
> >
> > [...]
>
> Applied to riscv-cache-for-next, thanks!
>
> [1/8] riscv: errata: Add StarFive JH7100 errata
> https://git.kernel.org/conor/c/64fc984a8a54
That's the one which also needs depends on !DMA_DIRECT_REMAP?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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