[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20231213-jester-rendering-dd876ef8e8ac@spud>
Date: Wed, 13 Dec 2023 15:42:44 +0000
From: Conor Dooley <conor@...nel.org>
To: linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Emil Renner Berthing <emil.renner.berthing@...onical.com>
Cc: conor@...nel.org, Conor Dooley <conor.dooley@...rochip.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Emil Renner Berthing <kernel@...il.dk>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Cristian Ciocaltea <cristian.ciocaltea@...labora.com>,
Geert Uytterhoeven <geert@...ux-m68k.org>
Subject: Re: (subset) [PATCH v2 0/8] Add JH7100 errata and update device tree
From: Conor Dooley <conor.dooley@...rochip.com>
On Thu, 30 Nov 2023 16:19:24 +0100, Emil Renner Berthing wrote:
> Now that the driver for the SiFive cache controller supports manual
> flushing as non-standard cache operations[1] we can add an errata option
> for the StarFive JH7100 SoC and update the device tree with the cache
> controller, dedicated DMA pool and add MMC nodes for the SD-card and
> wifi.
>
> This series needs the following commit in [1] to work properly:
>
> [...]
Applied to riscv-cache-for-next, thanks!
[1/8] riscv: errata: Add StarFive JH7100 errata
https://git.kernel.org/conor/c/64fc984a8a54
Thanks,
Conor.
Powered by blists - more mailing lists