linux-kernel - Re: [PATCH v2 1/8] riscv: errata: Add StarFive JH7100 errata

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 06 Dec 2023 09:09:30 -0800 (PST)
From:   Palmer Dabbelt <palmer@...belt.com>
To:     emil.renner.berthing@...onical.com
CC:     linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Paul Walmsley <paul.walmsley@...ive.com>, kernel@...il.dk,
        Conor Dooley <conor@...nel.org>, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org,
        cristian.ciocaltea@...labora.com, geert@...ux-m68k.org,
        Conor Dooley <conor.dooley@...rochip.com>
Subject:     Re: [PATCH v2 1/8] riscv: errata: Add StarFive JH7100 errata

On Thu, 30 Nov 2023 07:19:25 PST (-0800), emil.renner.berthing@...onical.com wrote:
> This not really an errata, but since the JH7100 was made before
> the standard Zicbom extension it needs the DMA_GLOBAL_POOL and
> RISCV_NONSTANDARD_CACHE_OPS enabled to work correctly.
>
> Acked-by: Conor Dooley <conor.dooley@...rochip.com>
> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@...onical.com>
> ---
>  arch/riscv/Kconfig.errata | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
>
> diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> index e2c731cfed8c..692de149141f 100644
> --- a/arch/riscv/Kconfig.errata
> +++ b/arch/riscv/Kconfig.errata
> @@ -53,6 +53,23 @@ config ERRATA_SIFIVE_CIP_1200
>
>  	  If you don't know what to do here, say "Y".
>
> +config ERRATA_STARFIVE_JH7100
> +	bool "StarFive JH7100 support"
> +	depends on ARCH_STARFIVE && NONPORTABLE
> +	select DMA_GLOBAL_POOL
> +	select RISCV_DMA_NONCOHERENT
> +	select RISCV_NONSTANDARD_CACHE_OPS
> +	select SIFIVE_CCACHE
> +	default n
> +	help
> +	  The StarFive JH7100 was a test chip for the JH7110 and has
> +	  caches that are non-coherent with respect to peripheral DMAs.
> +	  It was designed before the Zicbom extension so needs non-standard
> +	  cache operations through the SiFive cache controller.
> +
> +	  Say "Y" if you want to support the BeagleV Starlight and/or
> +	  StarFive VisionFive V1 boards.
> +
>  config ERRATA_THEAD
>  	bool "T-HEAD errata"
>  	depends on RISCV_ALTERNATIVE

Reviewed-by: Palmer Dabbelt <palmer@...osinc.com>
Acked-by: Palmer Dabbelt <palmer@...osinc.com>

Thanks for dealing with this.  This is mostly DT stuff so I'm fine with 
it going via Conor's tree, but LMK if you guys want me to take it.