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Message-ID: <1921146.taCxCBeP46@archlinux>
Date: Thu, 14 Dec 2023 18:15:01 +0100
From: Jernej Škrabec <jernej.skrabec@...il.com>
To: Andre Przywara <andre.przywara@....com>
Cc: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Chen-Yu Tsai <wens@...e.org>,
Samuel Holland <samuel@...lland.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
"Rafael J . Wysocki" <rafael@...nel.org>,
Viresh Kumar <viresh.kumar@...aro.org>,
Yangtao Li <tiny.windzz@...il.com>,
Brandon Cheo Fusi <fusibrandon13@...il.com>,
devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-sunxi@...ts.linux.dev,
linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org
Subject: Re: [PATCH 2/5] cpufreq: sun50i: Add D1 support
On Thursday, December 14, 2023 5:40:10 PM CET Andre Przywara wrote:
> On Thu, 14 Dec 2023 17:29:30 +0100
> Jernej Škrabec <jernej.skrabec@...il.com> wrote:
>
> Hi,
>
> > On Thursday, December 14, 2023 11:33:39 AM CET Brandon Cheo Fusi wrote:
> > > Add support for D1 based devices to the Allwinner H6 cpufreq
> > > driver
> > >
> > > Signed-off-by: Brandon Cheo Fusi <fusibrandon13@...il.com>
> > > ---
> > > drivers/cpufreq/sun50i-cpufreq-nvmem.c | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
> > > index 32a9c88f8..ccf83780f 100644
> > > --- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
> > > +++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
> > > @@ -160,6 +160,7 @@ static struct platform_driver sun50i_cpufreq_driver = {
> > >
> > > static const struct of_device_id sun50i_cpufreq_match_list[] = {
> > > { .compatible = "allwinner,sun50i-h6" },
> > > + { .compatible = "allwinner,sun20i-d1" },
> >
> > This is not needed, as there is no functionality change.
>
> That was my first reflex, too, but this is the *board* (fallback)
> compatible, listed in the root node, so you have to list it here for each
> SoC, together with the respective blocklist in the next patch.
> We are doing the same for the H616, and actually also need that for the
> H618. Weird, I know, but last time I check not easy to fix.
Oh, that's bad. What's the rationale to have so complicated probe method?
Why not using standard, compatible based one?
Best regards,
Jernej
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