linux-kernel - Re: [PATCH 1/5] riscv: dts: allwinner: Update opp table to allow CPU frequency scaling

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20231215151209.46221-1-fusibrandon13@gmail.com>
Date: Fri, 15 Dec 2023 16:12:09 +0100
From: Brandon Cheo Fusi <fusibrandon13@...il.com>
To: viresh.kumar@...aro.org
Cc: aou@...s.berkeley.edu,
	conor+dt@...nel.org,
	devicetree@...r.kernel.org,
	fusibrandon13@...il.com,
	jernej.skrabec@...il.com,
	krzysztof.kozlowski+dt@...aro.org,
	linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	linux-pm@...r.kernel.org,
	linux-riscv@...ts.infradead.org,
	linux-sunxi@...ts.linux.dev,
	palmer@...belt.com,
	paul.walmsley@...ive.com,
	rafael@...nel.org,
	robh+dt@...nel.org,
	samuel@...lland.org,
	tiny.windzz@...il.com,
	wens@...e.org
Subject: Re: [PATCH 1/5] riscv: dts: allwinner: Update opp table to allow CPU frequency scaling

On Thu, Dec 14, 2023 at 12:14 PM Viresh Kumar <viresh.kumar@...aro.org> wrote:
>
> On 14-12-23, 11:33, Brandon Cheo Fusi wrote:
> > Two OPPs are currently defined for the D1/D1s; one at 408MHz and
> > another at 1.08GHz. Switching between these can be done with the
> > "sun50i-cpufreq-nvmem" driver. This patch populates the opp table
> > appropriately, with inspiration from
> > https://github.com/Tina-Linux/linux-5.4/blob/master/arch/riscv/boot/dts/sunxi/sun20iw1p1.dtsi
> >
> > The supply voltages are PWM-controlled, but support for that IP
> > is still in the works. So stick to a fixed 0.9V vdd-cpu supply,
> > which seems to be the default on most D1 boards.
> >
> > Signed-off-by: Brandon Cheo Fusi <fusibrandon13@...il.com>
> > ---
> >  arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 18 +++++++++++++++---
> >  1 file changed, 15 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> > index 64c3c2e6c..e211fe4c7 100644
> > --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> > @@ -39,16 +39,22 @@ cpu0_intc: interrupt-controller {
> >       };
> >
> >       opp_table_cpu: opp-table-cpu {
> > -             compatible = "operating-points-v2";
> > +             compatible = "allwinner,sun20i-d1-operating-points",
>
> I don't think you should add a new compatible for every SoC that needs
> to be supported by a DT bindings and cpufreq driver. Maybe you should
> just reuse "allwinner,sun50i-h6-operating-points" and it will work
> fine for you ?
>
> Rob ?
>
> > +                              "allwinner,sun50i-h6-operating-points";
> > +             nvmem-cells = <&cpu_speed_grade>;
> > +             nvmem-cell-names = "speed";
> > +             opp-shared;
> >
> >               opp-408000000 {
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> >                       opp-hz = /bits/ 64 <408000000>;
> > -                     opp-microvolt = <900000 900000 1100000>;
> > +                     opp-microvolt-speed0 = <900000>;
>
> The separate property name thing was required when you could have
> different values for different SoC instances, which can be read from
> efuses, like in your case.
>
> But all I see is speed0 here, why don't you always set opp-microvolt
> then ?
>

Setting opp-microvolt would be ok, but opp-microvolt-speed0 was chosen for
consistency with the driver bindings here
https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml#L52 

> Also why degrade from min/max/target type to just target ?
>

This is a mistake on my part as I thought requesting non default voltages
was going to be a problem with lack of PWM support. Will be reverted in v2.

> >               };
> >
> >               opp-1080000000 {
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> >                       opp-hz = /bits/ 64 <1008000000>;
> > -                     opp-microvolt = <900000 900000 1100000>;
> > +                     opp-microvolt-speed0 = <900000>;
> >               };
> >       };
> >
> > @@ -115,3 +121,8 @@ pmu {
> >                       <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
> >       };
> >  };
> > +
> > +&sid {
> > +     cpu_speed_grade: cpu-speed-grade@0 {
> > +             reg = <0x00 0x2>;
> > +     };
> > +};
> > --
> > 2.30.2
>
> --
> viresh

Thank you for reviewing.
Brandon.