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Message-ID: <20231214062847.2215542-6-quic_ipkumar@quicinc.com>
Date: Thu, 14 Dec 2023 11:58:42 +0530
From: Praveenkumar I <quic_ipkumar@...cinc.com>
To: <agross@...nel.org>, <andersson@...nel.org>,
<konrad.dybcio@...aro.org>, <mturquette@...libre.com>,
<sboyd@...nel.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
<bhelgaas@...gle.com>, <lpieralisi@...nel.org>, <kw@...ux.com>,
<vkoul@...nel.org>, <kishon@...nel.org>, <mani@...nel.org>,
<quic_nsekar@...cinc.com>, <quic_srichara@...cinc.com>,
<linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-pci@...r.kernel.org>, <linux-phy@...ts.infradead.org>
CC: <quic_varada@...cinc.com>, <quic_devipriy@...cinc.com>,
<quic_kathirav@...cinc.com>, <quic_anusha@...cinc.com>
Subject: [PATCH 05/10] dt-bindings: phy: qcom,uniphy-pcie: Add ipq5332 bindings
Qualcomm IPQ5332 has single-lane and dual-lane PCIe UNIPHY
with Gen 3 support. This UNIPHY is similar to the one found
on Qualcomm IPQ5018. Hence add the bindings in qcom,uniphy-pcie.
Clocks and resets are different for IPQ5332. Update the
bindings to support both IPQ5018 and IPQ5332.
Signed-off-by: Praveenkumar I <quic_ipkumar@...cinc.com>
---
This patch depends on the below series which adds PCIe support in
Qualcomm IPQ5018
https://lore.kernel.org/all/20231003120846.28626-1-quic_nsekar@quicinc.com/
.../bindings/phy/qcom,uniphy-pcie-28lp.yaml | 65 +++++++++++++++++--
1 file changed, 58 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml b/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml
index 6b2574f9532e..205eaec2291e 100644
--- a/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,uniphy-pcie-28lp.yaml
@@ -20,19 +20,20 @@ properties:
maxItems: 1
clocks:
- maxItems: 1
+ minItems: 1
+ maxItems: 4
clock-names:
- items:
- - const: pipe_clk
+ minItems: 1
+ maxItems: 4
resets:
- maxItems: 2
+ minItems: 2
+ maxItems: 3
reset-names:
- items:
- - const: phy
- - const: phy_phy
+ minItems: 2
+ maxItems: 3
"#phy-cells":
const: 0
@@ -54,6 +55,56 @@ required:
- "#clock-cells"
- clock-output-names
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq5018-uniphy-pcie-gen2x1
+ - qcom,ipq5018-uniphy-pcie-gen2x2
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 1
+ clock-names:
+ items:
+ - const: pipe_clk
+ resets:
+ minItems: 2
+ maxItems: 2
+ reset-name:
+ items:
+ - const: phy
+ - const: phy_phy
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq5332-uniphy-pcie-gen3x1
+ - qcom,ipq5332-uniphy-pcie-gen3x2
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ maxItems: 4
+ clock-names:
+ items:
+ - const: pipe
+ - const: lane_m
+ - const: lane_s
+ - const: phy_ahb
+ resets:
+ minItems: 2
+ maxItems: 2
+ reset-name:
+ items:
+ - const: phy
+ - const: phy_ahb
+
additionalProperties: false
examples:
--
2.34.1
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