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Message-ID: <CAA8EJppV1UnC_Howfn1_4Ox-jftrRRF63QesFzqCSX+tC4c6FQ@mail.gmail.com>
Date: Thu, 14 Dec 2023 09:12:39 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Praveenkumar I <quic_ipkumar@...cinc.com>
Cc: agross@...nel.org, andersson@...nel.org, konrad.dybcio@...aro.org,
mturquette@...libre.com, sboyd@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
bhelgaas@...gle.com, lpieralisi@...nel.org, kw@...ux.com,
vkoul@...nel.org, kishon@...nel.org, mani@...nel.org,
quic_nsekar@...cinc.com, quic_srichara@...cinc.com,
linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org, linux-phy@...ts.infradead.org,
quic_varada@...cinc.com, quic_devipriy@...cinc.com,
quic_kathirav@...cinc.com, quic_anusha@...cinc.com
Subject: Re: [PATCH 04/10] phy: qcom: Add support for Pipe clock rate from
device data
On Thu, 14 Dec 2023 at 08:29, Praveenkumar I <quic_ipkumar@...cinc.com> wrote:
>
> Qualcomm IPQ5332 has the same PCIe UNIPHY PHY with different pipe
> clock rate. Add support to define the pipe clock rate in device
> data.
>
> Signed-off-by: Praveenkumar I <quic_ipkumar@...cinc.com>
With the name fixed:
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> ---
> This patch depends on the below series which adds PCIe support in
> Qualcomm IPQ5018
> https://lore.kernel.org/all/20231003120846.28626-1-quic_nsekar@quicinc.com/
>
> drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
> index 5ef6ae7276cf..9f9a03faf6fa 100644
> --- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
> @@ -54,6 +54,7 @@ struct uniphy_pcie_data {
> unsigned int phy_type;
> const struct uniphy_regs *init_seq;
> unsigned int init_seq_num;
> + unsigned int pipe_clk_rate;
> };
>
> struct qcom_uniphy_pcie {
> @@ -117,6 +118,7 @@ static const struct uniphy_pcie_data ipq5018_2x2_data = {
> .phy_type = PHY_TYPE_PCIE_GEN2,
> .init_seq = ipq5018_regs,
> .init_seq_num = ARRAY_SIZE(ipq5018_regs),
> + .pipe_clk_rate = 125000000,
> };
>
> static void qcom_uniphy_pcie_init(struct qcom_uniphy_pcie *phy)
> @@ -232,6 +234,7 @@ static int qcom_uniphy_pcie_get_resources(struct platform_device *pdev,
> static int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy,
> struct device_node *np)
> {
> + const struct uniphy_pcie_data *data = phy->data;
> struct clk_fixed_rate *fixed;
> struct clk_init_data init = { };
> int ret;
> @@ -247,7 +250,7 @@ static int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy,
> return -ENOMEM;
>
> init.ops = &clk_fixed_rate_ops;
> - fixed->fixed_rate = 125000000;
> + fixed->fixed_rate = data->pipe_clk_rate;
> fixed->hw.init = &init;
>
> ret = devm_clk_hw_register(phy->dev, &fixed->hw);
> --
> 2.34.1
>
>
--
With best wishes
Dmitry
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