linux-kernel - Re: [PATCH] dt-bindings: riscv: cpus: Add AMD MicroBlaze V compatible

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Message-ID: <e9d531bf-a0f5-407d-9d73-97c966b89fd7@amd.com>
Date: Wed, 20 Dec 2023 14:50:25 +0100
From: Michal Simek <michal.simek@....com>
To: linux-kernel@...r.kernel.org, monstr@...str.eu, michal.simek@...inx.com,
 git@...inx.com, Conor Dooley <conor+dt@...nel.org>
Cc: Albert Ou <aou@...s.berkeley.edu>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
 Palmer Dabbelt <palmer@...belt.com>, Paul Walmsley
 <paul.walmsley@...ive.com>, Rob Herring <robh+dt@...nel.org>,
 devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org
Subject: Re: [PATCH] dt-bindings: riscv: cpus: Add AMD MicroBlaze V compatible

Hi Conor,

On 11/6/23 12:37, Michal Simek wrote:
> MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
> It is hardware compatible with classic MicroBlaze processor.
> 
> Signed-off-by: Michal Simek <michal.simek@....com>
> ---
> 
>   Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 97e8441eda1c..7b077af62b27 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -32,6 +32,7 @@ properties:
>       oneOf:
>         - items:
>             - enum:
> +              - amd,mbv32
>                 - andestech,ax45mp
>                 - canaan,k210
>                 - sifive,bullet0

Can you please queue this patch to your tree?

Thanks,
Michal