linux-kernel - [RFC PATCH 1/2] phy: ti: gmii-sel: Enable SGMII mode for J784S4

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Date: Thu, 21 Dec 2023 15:59:55 +0530
From: Chintan Vankar <c-vankar@...com>
To: Maxime Ripard <mripard@...nel.org>,
        Uwe Kleine-König
	<u.kleine-koenig@...gutronix.de>,
        Sinthu Raja <sinthu.raja@...com>, Chintan
 Vankar <c-vankar@...com>,
        Andrew Davis <afd@...com>, Siddharth Vadapalli
	<s-vadapalli@...com>,
        Roger Quadros <rogerq@...nel.org>,
        Kishon Vijay Abraham
 I <kishon@...nel.org>,
        Vinod Koul <vkoul@...nel.org>
CC: <linux-kernel@...r.kernel.org>, <linux-phy@...ts.infradead.org>
Subject: [RFC PATCH 1/2] phy: ti: gmii-sel: Enable SGMII mode for J784S4

TI's J784S4 SoC supports SGMII mode with the CPSW9G instance of the CPSW
Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the
corresponding extra_modes member.

Signed-off-by: Chintan Vankar <c-vankar@...com>
---
 drivers/phy/ti/phy-gmii-sel.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
index bc847d3879f7..0f4818adb440 100644
--- a/drivers/phy/ti/phy-gmii-sel.c
+++ b/drivers/phy/ti/phy-gmii-sel.c
@@ -248,7 +248,7 @@ static const
 struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = {
 	.use_of_data = true,
 	.regfields = phy_gmii_sel_fields_am654,
-	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) |
+	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) |
 		       BIT(PHY_INTERFACE_MODE_USXGMII),
 	.num_ports = 8,
 	.num_qsgmii_main_ports = 2,
-- 
2.34.1