linux-kernel - RE: [PATCH v4 1/2] riscv: introduce RISCV_EFFICIENT_UNALIGNED

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Date: Wed, 27 Dec 2023 10:41:53 +0000
From: David Laight <David.Laight@...LAB.COM>
To: 'Jisheng Zhang' <jszhang@...nel.org>, Paul Walmsley
	<paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, Albert Ou
	<aou@...s.berkeley.edu>
CC: "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, Eric Biggers
	<ebiggers@...nel.org>, Conor Dooley <conor.dooley@...rochip.com>, "Qingfang
 DENG" <dqfext@...il.com>, Charlie Jenkins <charlie@...osinc.com>
Subject: RE: [PATCH v4 1/2] riscv: introduce RISCV_EFFICIENT_UNALIGNED_ACCESS

From: Jisheng Zhang
> Sent: 25 December 2023 04:42
> 
> Some riscv implementations such as T-HEAD's C906, C908, C910 and C920
> support efficient unaligned access, for performance reason we want
> to enable HAVE_EFFICIENT_UNALIGNED_ACCESS on these platforms. To
> avoid performance regressions on other non efficient unaligned access
> platforms, HAVE_EFFICIENT_UNALIGNED_ACCESS can't be globally selected.

How efficient are these EFFICIENT_UNALIGNED_ACCESS ?

For single word accesses it doesn't matter much (since they don't fault).
But for memcpy() (and similar) if they are slightly slow (eg the same
as two aligned accesses) it is likely still worth doing misaligned
transfers for both ends and aligned transfers for the middle.

For example, on modern x86 it really isn't worth worrying about
misaligned transfers of 64bit registers.
AFAICT accesses within a cacheline just use byte enables - so are zero
cost. Accesses that cross cache line boundaries do get split - but the
out-of-order execute, store-buffer and the ability to do two reads in
each clock cycle make the overall cost only just measurable.

Not sure how the various RISC-V cpu compare though.
You might get an extra clock delay a lot more often.
So, while mostly you 'don't care' about the alignment, there may
still be a few places where it does matter.

	David

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