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Message-ID: <75fd794c-0366-445b-aa69-0975afb247c7@linaro.org> Date: Wed, 27 Dec 2023 13:40:59 +0100 From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org> To: Elad Nachman <enachman@...vell.com>, robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org, andrew@...n.ch, gregory.clement@...tlin.com, sebastian.hesselbarth@...il.com, huziji@...vell.com, ulf.hansson@...aro.org, catalin.marinas@....com, will@...nel.org, adrian.hunter@...el.com, thunder.leizhen@...wei.com, bhe@...hat.com, akpm@...ux-foundation.org, yajun.deng@...ux.dev, chris.zjh@...wei.com, linux-mmc@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org Cc: cyuval@...vell.com Subject: Re: [PATCH 3/4] arm64: dts: ac5: add mmc node and clock On 27/12/2023 13:32, Elad Nachman wrote: > From: Elad Nachman <enachman@...vell.com> > > Add mmc and mmc clock nodes to ac5 and ac5x device tree files > > Signed-off-by: Elad Nachman <enachman@...vell.com> > --- > arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 33 ++++++++++++++++++- > 1 file changed, 32 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi > index b5e042b8e929..decad14d0db8 100644 > --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi > +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi > @@ -77,7 +77,6 @@ soc { > #address-cells = <2>; > #size-cells = <2>; > ranges; > - dma-ranges; > > internal-regs@...00000 { > #address-cells = <1>; > @@ -204,6 +203,31 @@ gpio1: gpio@...40 { > }; > }; > > + mmc_dma: mmc-dma-peripherals@...00000 { Generic node name, so bus@? > + compatible = "simple-bus"; > + #address-cells = <0x2>; > + #size-cells = <0x2>; > + ranges; ranges is second. You have address/size cells, so are you sure dtbs W=1 does not complain? > + dma-ranges = <0x0 0x0 0x2 0x0 0x0 0x80000000>; > + dma-coherent; > + > + sdhci: mmc@...c0000 { > + compatible = "marvell,ac5-sdhci", > + "marvell,armada-ap806-sdhci"; > + reg = <0x0 0x805c0000 0x0 0x1000>; > + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&emmc_clock>, <&cnm_clock>; > + clock-names = "core", "axi"; > + status = "okay"; Drop > + bus-width = <8>; > + /*marvell,xenon-phy-slow-mode;*/ Drop or explain why commented code should be here. > + non-removable; > + mmc-ddr-1_8v; > + mmc-hs200-1_8v; > + mmc-hs400-1_8v; > + }; > + }; > + > /* > * Dedicated section for devices behind 32bit controllers so we > * can configure specific DMA mapping for them > @@ -335,5 +359,12 @@ nand_clock: nand-clock { > #clock-cells = <0>; > clock-frequency = <400000000>; > }; > + > + emmc_clock: emmc_clock { No underscores in node names. I think you got such feedback before. But anyway, this looks like a fake clock. > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <400000000>; > + }; > + Drop > }; > }; Best regards, Krzysztof
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