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Message-Id: <20231227-topic-8280_pcie_dts-v1-1-13d12b1698ff@linaro.org> Date: Wed, 27 Dec 2023 23:28:26 +0100 From: Konrad Dybcio <konrad.dybcio@...aro.org> To: Bjorn Andersson <andersson@...nel.org>, Rob Herring <robh+dt@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>, Johan Hovold <johan+linaro@...nel.org> Cc: Marijn Suijten <marijn.suijten@...ainline.org>, linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>, Konrad Dybcio <konrad.dybcio@...ainline.org>, Konrad Dybcio <konrad.dybcio@...aro.org> Subject: [PATCH 1/3] arm64: dts: qcom: sc8280xp: Fix PCIe PHY power-domains The PCIe GDSCs are only related to the RCs. The PCIe PHYs on the other hand, are powered by VDD_MX and their specific VDDA_PHY/PLL regulators. Fix the power-domains assignment to stop potentially toggling the GDSC unnecessarily. Fixes: 813e83157001 ("arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes") Signed-off-by: Konrad Dybcio <konrad.dybcio@...aro.org> --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index febf28356ff8..72c5818b67f2 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1797,7 +1797,7 @@ pcie4_phy: phy@...6000 { assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; - power-domains = <&gcc PCIE_4_GDSC>; + power-domains = <&rpmhpd SC8280XP_MX>; resets = <&gcc GCC_PCIE_4_PHY_BCR>; reset-names = "phy"; @@ -1895,7 +1895,7 @@ pcie3b_phy: phy@...e000 { assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; - power-domains = <&gcc PCIE_3B_GDSC>; + power-domains = <&rpmhpd SC8280XP_MX>; resets = <&gcc GCC_PCIE_3B_PHY_BCR>; reset-names = "phy"; @@ -1994,7 +1994,7 @@ pcie3a_phy: phy@...4000 { assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; - power-domains = <&gcc PCIE_3A_GDSC>; + power-domains = <&rpmhpd SC8280XP_MX>; resets = <&gcc GCC_PCIE_3A_PHY_BCR>; reset-names = "phy"; @@ -2094,7 +2094,7 @@ pcie2b_phy: phy@...e000 { assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; - power-domains = <&gcc PCIE_2B_GDSC>; + power-domains = <&rpmhpd SC8280XP_MX>; resets = <&gcc GCC_PCIE_2B_PHY_BCR>; reset-names = "phy"; @@ -2193,7 +2193,7 @@ pcie2a_phy: phy@...4000 { assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; - power-domains = <&gcc PCIE_2A_GDSC>; + power-domains = <&rpmhpd SC8280XP_MX>; resets = <&gcc GCC_PCIE_2A_PHY_BCR>; reset-names = "phy"; -- 2.43.0
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