linux-kernel - Re: [PATCH v8 09/10] iommufd: Add data structure for Intel VT-d stage-1 cache invalidation

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Message-ID: <9be98837-b656-49e5-8ae6-d70ad2c073b4@intel.com>
Date: Thu, 28 Dec 2023 16:35:13 +0800
From: Yi Liu <yi.l.liu@...el.com>
To: "Tian, Kevin" <kevin.tian@...el.com>, "joro@...tes.org" <joro@...tes.org>,
	"alex.williamson@...hat.com" <alex.williamson@...hat.com>, "jgg@...dia.com"
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	"baolu.lu@...ux.intel.com" <baolu.lu@...ux.intel.com>
CC: "cohuck@...hat.com" <cohuck@...hat.com>, "eric.auger@...hat.com"
	<eric.auger@...hat.com>, "nicolinc@...dia.com" <nicolinc@...dia.com>,
	"kvm@...r.kernel.org" <kvm@...r.kernel.org>, "mjrosato@...ux.ibm.com"
	<mjrosato@...ux.ibm.com>, "chao.p.peng@...ux.intel.com"
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	"linux-kselftest@...r.kernel.org" <linux-kselftest@...r.kernel.org>, "Duan,
 Zhenzhong" <zhenzhong.duan@...el.com>, "joao.m.martins@...cle.com"
	<joao.m.martins@...cle.com>, "Zeng, Xin" <xin.zeng@...el.com>, "Zhao, Yan Y"
	<yan.y.zhao@...el.com>, "j.granados@...sung.com" <j.granados@...sung.com>
Subject: Re: [PATCH v8 09/10] iommufd: Add data structure for Intel VT-d
 stage-1 cache invalidation

On 2023/12/28 14:38, Tian, Kevin wrote:
>> From: Tian, Kevin
>> Sent: Thursday, December 28, 2023 2:38 PM
>>
>>> From: Liu, Yi L <yi.l.liu@...el.com>
>>> Sent: Thursday, December 28, 2023 12:14 AM
>>> +/**
>>> + * struct iommu_hwpt_vtd_s1_invalidate - Intel VT-d cache invalidation
>>> + *                                       (IOMMU_HWPT_INVALIDATE_DATA_VTD_S1)
>>> + * @addr: The start address of the range to be invalidated. It needs to
>>> + *        be 4KB aligned.
>>> + * @npages: Number of contiguous 4K pages to be invalidated.
>>> + * @flags: Combination of enum iommu_hwpt_vtd_s1_invalidate_flags
>>> + * @hw_error: One of enum iommu_hwpt_vtd_s1_invalidate_error
>>> + *
>>> + * The Intel VT-d specific invalidation data for user-managed stage-1 cache
>>> + * invalidation in nested translation. Userspace uses this structure to
>>> + * tell the impacted cache scope after modifying the stage-1 page table.
>>> + *
>>> + * Invalidating all the caches related to the page table by setting @addr
>>> + * to be 0 and @npages to be U64_MAX.
>>> + *
>>> + * The device TLB will be invalidated automatically if ATS is enabled.
>>> + *
>>> + * The @hw_error is meaningful when the entry is handled by the kernel.
>>> + * Check the entry_num output of IOMMU_HWPT_INVALIDATE ioctl to
>>> know the
>>> + * handled entries. @hw_error only covers the errors detected by
>> hardware.
>>> + * The software detected errors would go through the normal ioctl errno.
>>> + */
>>
>> * An entry is considered 'handled' after it passes the audit and submitted
>> * to the IOMMU by the underlying driver. Check the @entry_num output of
>> * struct iommu_hwpt_invalidate for the number of handled entries. A
>> 'handled'
>> * request may still fail in hardware for various reasons, e.g. due to timeout
>> * on waiting for device response upon a device TLB invalidation request. In
>> * such case the hardware error info is reported in the @hw_error field of the
>> * handled entry.
> 
> with that:
> 
> Reviewed-by: Kevin Tian <kevin.tian@...el.com>

yep.

-- 
Regards,
Yi Liu