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Message-ID: <160a7f08-1e73-4468-80d8-6ac5974d81d3@linux.intel.com>
Date: Thu, 28 Dec 2023 21:20:35 +0800
From: Ethan Zhao <haifeng.zhao@...ux.intel.com>
To: "Tian, Kevin" <kevin.tian@...el.com>,
 "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
 "baolu.lu@...ux.intel.com" <baolu.lu@...ux.intel.com>,
 "dwmw2@...radead.org" <dwmw2@...radead.org>,
 "will@...nel.org" <will@...nel.org>,
 "robin.murphy@....com" <robin.murphy@....com>,
 "lukas@...ner.de" <lukas@...ner.de>
Cc: "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
 "iommu@...ts.linux.dev" <iommu@...ts.linux.dev>,
 "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [RFC PATCH v9 1/5] iommu/vt-d: add flush_target_dev member to
 struct intel_iommu and pass device info to all ATS Invalidation functions


On 12/28/2023 4:10 PM, Tian, Kevin wrote:
>> From: Ethan Zhao <haifeng.zhao@...ux.intel.com>
>> Sent: Thursday, December 28, 2023 8:17 AM
>>
>> @@ -181,6 +181,7 @@ static void __flush_svm_range_dev(struct intel_svm
>> *svm,
>>
>>   	qi_flush_piotlb(sdev->iommu, sdev->did, svm->pasid, address, pages,
>> ih);
>>   	if (info->ats_enabled) {
>> +		info->iommu->flush_target_dev = info->dev;
>>   		qi_flush_dev_iotlb_pasid(sdev->iommu, sdev->sid, info-
>>> pfsid,
>>   					 svm->pasid, sdev->qdep, address,
>>   					 order_base_2(pages));
> this is wrong both in concept and function.
Yes, wrong.
>
> an iommu instance can be shared by many devices which may all have
> ongoing ATS invalidation requests to handle. Using a per-iommu field
> to store the flush target is limiting (and there is no lock protection at all).
>
> if there is a real need of passing dev pointer to qi helpers, just change
> the helper to accept an explicit parameter.

seems the only way is to add parameter and refactor all affected

functions.


Thanks,

Ethan


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