lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Message-ID: <20231229065405.235625-2-jeeheng.sia@starfivetech.com> Date: Fri, 29 Dec 2023 14:54:05 +0800 From: Sia Jee Heng <jeeheng.sia@...rfivetech.com> To: <linux-kernel@...r.kernel.org>, <linux-riscv@...ts.infradead.org> CC: <rafael.j.wysocki@...el.com>, <ajones@...tanamicro.com>, <conor.dooley@...rochip.com>, <sunilvl@...tanamicro.com>, <jeeheng.sia@...rfivetech.com>, <aou@...s.berkeley.edu>, <palmer@...belt.com>, <paul.walmsley@...ive.com> Subject: [RFC v1 1/1] RISC-V: ACPI: Enable SPCR table for console output on RISC-V The ACPI SPCR code has been used to enable console output for ARM64 and X86. The same code can be reused for RISC-V. Vendor will enable/disable the SPCR table in the firmware based on the platform design. However, in cases where the SPCR table is not usable, a kernel parameter could be used to specify the preferred console. Signed-off-by: Sia Jee Heng <jeeheng.sia@...rfivetech.com> --- arch/riscv/kernel/acpi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c index e619edc8b0cc..5ec2fdf9e09f 100644 --- a/arch/riscv/kernel/acpi.c +++ b/arch/riscv/kernel/acpi.c @@ -18,6 +18,7 @@ #include <linux/io.h> #include <linux/memblock.h> #include <linux/pci.h> +#include <linux/serial_core.h> int acpi_noirq = 1; /* skip ACPI IRQ initialization */ int acpi_disabled = 1; @@ -151,6 +152,9 @@ void __init acpi_boot_table_init(void) if (!param_acpi_force) disable_acpi(); } + + if (!acpi_disabled) + acpi_parse_spcr(earlycon_acpi_spcr_enable, true); } static int acpi_parse_madt_rintc(union acpi_subtable_headers *header, const unsigned long end) -- 2.34.1
Powered by blists - more mailing lists