lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20240102-1ddc9ec273fded1548ee586d@orel>
Date: Tue, 2 Jan 2024 16:39:06 +0100
From: Andrew Jones <ajones@...tanamicro.com>
To: Sia Jee Heng <jeeheng.sia@...rfivetech.com>
Cc: linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org, 
	rafael.j.wysocki@...el.com, conor.dooley@...rochip.com, sunilvl@...tanamicro.com, 
	aou@...s.berkeley.edu, palmer@...belt.com, paul.walmsley@...ive.com
Subject: Re: [RFC v1 1/1] RISC-V: ACPI: Enable SPCR table for console output
 on RISC-V

On Fri, Dec 29, 2023 at 02:54:05PM +0800, Sia Jee Heng wrote:
> The ACPI SPCR code has been used to enable console output for ARM64 and
> X86. The same code can be reused for RISC-V.
> 
> Vendor will enable/disable the SPCR table in the firmware based on the
> platform design. However, in cases where the SPCR table is not usable,
> a kernel parameter could be used to specify the preferred console.
> 
> Signed-off-by: Sia Jee Heng <jeeheng.sia@...rfivetech.com>
> ---
>  arch/riscv/kernel/acpi.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c
> index e619edc8b0cc..5ec2fdf9e09f 100644
> --- a/arch/riscv/kernel/acpi.c
> +++ b/arch/riscv/kernel/acpi.c
> @@ -18,6 +18,7 @@
>  #include <linux/io.h>
>  #include <linux/memblock.h>
>  #include <linux/pci.h>
> +#include <linux/serial_core.h>
>  
>  int acpi_noirq = 1;		/* skip ACPI IRQ initialization */
>  int acpi_disabled = 1;
> @@ -151,6 +152,9 @@ void __init acpi_boot_table_init(void)
>  		if (!param_acpi_force)
>  			disable_acpi();
>  	}
> +
> +	if (!acpi_disabled)
> +		acpi_parse_spcr(earlycon_acpi_spcr_enable, true);

Both arm64 and loongarch call early_init_dt_scan_chosen_stdout() when
acpi_disabled and earlycon_acpi_spcr_enable are both true. Is that
not necessary for RISC-V?

Thanks,
drew

>  }
>  
>  static int acpi_parse_madt_rintc(union acpi_subtable_headers *header, const unsigned long end)
> -- 
> 2.34.1
> 

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ