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Message-Id: <20231229074508.2709093-2-JJLIU0@nuvoton.com> Date: Fri, 29 Dec 2023 15:45:06 +0800 From: jim.t90615@...il.com To: JJLIU0@...oton.com, KWLIU@...oton.com, jim.t90615@...il.com, linus.walleij@...aro.org, brgl@...ev.pl, andy@...nel.org, robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org Cc: linux-gpio@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, openbmc@...ts.ozlabs.org, Rob Herring <robh@...nel.org>, Paul Menzel <pmenzel@...gen.mpg.de> Subject: [PATCH v10 1/3] dt-bindings: gpio: add NPCM sgpio driver bindings From: Jim Liu <JJLIU0@...oton.com> Add dt-bindings document for the Nuvoton NPCM7xx sgpio driver Signed-off-by: Jim Liu <JJLIU0@...oton.com> Reviewed-by: Linus Walleij <linus.walleij@...aro.org> Reviewed-by: Rob Herring <robh@...nel.org> Reviewed-by: Paul Menzel <pmenzel@...gen.mpg.de> --- Changes for v10: - modify error words Changes for v9: - no changed Changes for v8: - no changed --- .../bindings/gpio/nuvoton,sgpio.yaml | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/nuvoton,sgpio.yaml diff --git a/Documentation/devicetree/bindings/gpio/nuvoton,sgpio.yaml b/Documentation/devicetree/bindings/gpio/nuvoton,sgpio.yaml new file mode 100644 index 000000000000..9e32e54aeb24 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/nuvoton,sgpio.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/nuvoton,sgpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton SGPIO controller + +maintainers: + - Jim LIU <JJLIU0@...oton.com> + +description: | + This SGPIO controller is for NUVOTON NPCM7xx and NPCM8xx SoC and detailed + information is in the NPCM7XX/8XX SERIAL I/O EXPANSION INTERFACE section. + Nuvoton NPCM7xx SGPIO module is combines a serial to parallel IC (HC595) + and a parallel to serial IC (HC165). + Clock is a division of the APB3 clock. + This interface has 4 pins (D_out , D_in, S_CLK, LDSH). + NPCM7xx/NPCM8xx have two sgpio modules. Each module can support up + to 64 output pins, and up to 64 input pins, the pin is only for GPI or GPO. + GPIO pins can be programmed to support the following options + - Support interrupt option for each input port and various interrupt + sensitivity options (level-high, level-low, edge-high, edge-low) + - ngpios is number of nuvoton,input-ngpios GPIO lines and nuvoton,output-ngpios GPIO lines. + nuvoton,input-ngpios GPIO lines is only for GPI. + nuvoton,output-ngpios GPIO lines is only for GPO. + +properties: + compatible: + enum: + - nuvoton,npcm750-sgpio + - nuvoton,npcm845-sgpio + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + nuvoton,input-ngpios: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The numbers of GPIO's exposed. GPIO lines are only for GPI. + minimum: 0 + maximum: 64 + + nuvoton,output-ngpios: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The numbers of GPIO's exposed. GPIO lines are only for GPO. + minimum: 0 + maximum: 64 + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - interrupts + - nuvoton,input-ngpios + - nuvoton,output-ngpios + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + gpio8: gpio@...000 { + compatible = "nuvoton,npcm750-sgpio"; + reg = <0x101000 0x200>; + clocks = <&clk NPCM7XX_CLK_APB3>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + nuvoton,input-ngpios = <64>; + nuvoton,output-ngpios = <64>; + }; -- 2.25.1
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