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Message-Id: <20231229075739.8328-2-zajec5@gmail.com>
Date: Fri, 29 Dec 2023 08:57:39 +0100
From: Rafał Miłecki <zajec5@...il.com>
To: Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Cc: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Rafał Miłecki <rafal@...ecki.pl>
Subject: [PATCH 2/2] arm64: dts: mediatek: mt7986: reorder nodes
From: Rafał Miłecki <rafal@...ecki.pl>
Use order described as preferred in DTS Coding Style:
1. Sort bus nodes by unit address
2. Use alpha-numerical order for the rest
Signed-off-by: Rafał Miłecki <rafal@...ecki.pl>
---
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 118 +++++++++++-----------
1 file changed, 59 insertions(+), 59 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
index 23feeff881de..a0f28b9ada18 100644
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -16,13 +16,6 @@ / {
#address-cells = <2>;
#size-cells = <2>;
- clk40m: oscillator-40m {
- compatible = "fixed-clock";
- clock-frequency = <40000000>;
- #clock-cells = <0>;
- clock-output-names = "clkxtal";
- };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -59,6 +52,13 @@ cpu3: cpu@3 {
};
};
+ clk40m: oscillator-40m {
+ compatible = "fixed-clock";
+ clock-frequency = <40000000>;
+ #clock-cells = <0>;
+ clock-output-names = "clkxtal";
+ };
+
psci {
compatible = "arm,psci-0.2";
method = "smc";
@@ -121,15 +121,6 @@ wo_boot: wo-boot@...94000 {
};
- timer {
- compatible = "arm,armv8-timer";
- interrupt-parent = <&gic>;
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
- };
-
soc {
compatible = "simple-bus";
ranges;
@@ -202,6 +193,20 @@ pio: pinctrl@...1f000 {
#interrupt-cells = <2>;
};
+ pwm: pwm@...48000 {
+ compatible = "mediatek,mt7986-pwm";
+ reg = <0 0x10048000 0 0x1000>;
+ #clock-cells = <1>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_PWM_SEL>,
+ <&infracfg CLK_INFRA_PWM_STA>,
+ <&infracfg CLK_INFRA_PWM1_CK>,
+ <&infracfg CLK_INFRA_PWM2_CK>;
+ clock-names = "top", "main", "pwm1", "pwm2";
+ status = "disabled";
+ };
+
sgmiisys0: syscon@...60000 {
compatible = "mediatek,mt7986-sgmiisys_0",
"syscon";
@@ -240,20 +245,6 @@ crypto: crypto@...20000 {
status = "disabled";
};
- pwm: pwm@...48000 {
- compatible = "mediatek,mt7986-pwm";
- reg = <0 0x10048000 0 0x1000>;
- #clock-cells = <1>;
- #pwm-cells = <2>;
- interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CLK_TOP_PWM_SEL>,
- <&infracfg CLK_INFRA_PWM_STA>,
- <&infracfg CLK_INFRA_PWM1_CK>,
- <&infracfg CLK_INFRA_PWM2_CK>;
- clock-names = "top", "main", "pwm1", "pwm2";
- status = "disabled";
- };
-
uart0: serial@...02000 {
compatible = "mediatek,mt7986-uart",
"mediatek,mt6577-uart";
@@ -337,6 +328,21 @@ spi1: spi@...0b000 {
status = "disabled";
};
+ thermal: thermal@...0c800 {
+ compatible = "mediatek,mt7986-thermal";
+ reg = <0 0x1100c800 0 0x800>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_THERM_CK>,
+ <&infracfg CLK_INFRA_ADC_26M_CK>,
+ <&infracfg CLK_INFRA_ADC_FRC_CK>;
+ clock-names = "therm", "auxadc", "adc_32k";
+ nvmem-cells = <&thermal_calibration>;
+ nvmem-cell-names = "calibration-data";
+ #thermal-sensor-cells = <1>;
+ mediatek,auxadc = <&auxadc>;
+ mediatek,apmixedsys = <&apmixedsys>;
+ };
+
auxadc: adc@...0d000 {
compatible = "mediatek,mt7986-auxadc";
reg = <0 0x1100d000 0 0x1000>;
@@ -388,21 +394,6 @@ mmc0: mmc@...30000 {
status = "disabled";
};
- thermal: thermal@...0c800 {
- compatible = "mediatek,mt7986-thermal";
- reg = <0 0x1100c800 0 0x800>;
- interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CLK_INFRA_THERM_CK>,
- <&infracfg CLK_INFRA_ADC_26M_CK>,
- <&infracfg CLK_INFRA_ADC_FRC_CK>;
- clock-names = "therm", "auxadc", "adc_32k";
- nvmem-cells = <&thermal_calibration>;
- nvmem-cell-names = "calibration-data";
- #thermal-sensor-cells = <1>;
- mediatek,auxadc = <&auxadc>;
- mediatek,apmixedsys = <&apmixedsys>;
- };
-
pcie: pcie@...80000 {
compatible = "mediatek,mt7986-pcie",
"mediatek,mt8192-pcie";
@@ -534,20 +525,6 @@ wed1: wed@...11000 {
mediatek,wo-ccif = <&wo_ccif1>;
};
- wo_ccif0: syscon@...a5000 {
- compatible = "mediatek,mt7986-wo-ccif", "syscon";
- reg = <0 0x151a5000 0 0x1000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- wo_ccif1: syscon@...ad000 {
- compatible = "mediatek,mt7986-wo-ccif", "syscon";
- reg = <0 0x151ad000 0 0x1000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
- };
-
eth: ethernet@...00000 {
compatible = "mediatek,mt7986-eth";
reg = <0 0x15100000 0 0x80000>;
@@ -590,6 +567,20 @@ eth: ethernet@...00000 {
status = "disabled";
};
+ wo_ccif0: syscon@...a5000 {
+ compatible = "mediatek,mt7986-wo-ccif", "syscon";
+ reg = <0 0x151a5000 0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ wo_ccif1: syscon@...ad000 {
+ compatible = "mediatek,mt7986-wo-ccif", "syscon";
+ reg = <0 0x151ad000 0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
wifi: wifi@...00000 {
compatible = "mediatek,mt7986-wmac";
reg = <0 0x18000000 0 0x1000000>,
@@ -647,4 +638,13 @@ cpu_trip_active_low: active-low {
};
};
};
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
};
--
2.35.3
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