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Message-Id: <66a3c846d26ab73227dfcd141d021a46cad6672b.1704790558.git.unicorn_wang@outlook.com>
Date: Tue, 9 Jan 2024 17:17:33 +0800
From: Chen Wang <unicornxw@...il.com>
To: aou@...s.berkeley.edu,
chao.wei@...hgo.com,
conor@...nel.org,
krzysztof.kozlowski+dt@...aro.org,
palmer@...belt.com,
paul.walmsley@...ive.com,
robh+dt@...nel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org,
haijiao.liu@...hgo.com,
xiaoguang.xing@...hgo.com,
guoren@...nel.org,
jszhang@...nel.org,
inochiama@...look.com
Cc: Chen Wang <unicorn_wang@...look.com>
Subject: [PATCH 3/4] riscv: dts: add reset generator for Sophgo SG2042 SoC
From: Chen Wang <unicorn_wang@...look.com>
Add reset generator node to device tree for SG2042.
Signed-off-by: Chen Wang <unicorn_wang@...look.com>
---
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index 93256540d078..f59081d4f0ee 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -6,6 +6,8 @@
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/reset/sophgo,sg2042-reset.h>
+
#include "sg2042-cpus.dtsi"
/ {
@@ -311,6 +313,12 @@ intc: interrupt-controller@...0000000 {
riscv,ndev = <224>;
};
+ rstgen: reset-controller@...0013000 {
+ compatible = "sophgo,sg2042-reset";
+ reg = <0x00000070 0x30013000 0x00000000 0x0000000c>;
+ #reset-cells = <1>;
+ };
+
uart0: serial@...0000000 {
compatible = "snps,dw-apb-uart";
reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
--
2.25.1
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