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Message-Id: <18e1093a7f1357af7d9e9df12ede2e99725632e3.1704790558.git.unicorn_wang@outlook.com>
Date: Tue, 9 Jan 2024 17:17:51 +0800
From: Chen Wang <unicornxw@...il.com>
To: aou@...s.berkeley.edu,
chao.wei@...hgo.com,
conor@...nel.org,
krzysztof.kozlowski+dt@...aro.org,
palmer@...belt.com,
paul.walmsley@...ive.com,
robh+dt@...nel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org,
haijiao.liu@...hgo.com,
xiaoguang.xing@...hgo.com,
guoren@...nel.org,
jszhang@...nel.org,
inochiama@...look.com
Cc: Chen Wang <unicorn_wang@...look.com>
Subject: [PATCH 4/4] riscv: dts: add resets property for uart node
From: Chen Wang <unicorn_wang@...look.com>
Add resets property for uart0 for completeness, although it is
deasserted by default.
Signed-off-by: Chen Wang <unicorn_wang@...look.com>
---
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index f59081d4f0ee..03266f216021 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -327,6 +327,7 @@ uart0: serial@...0000000 {
clock-frequency = <500000000>;
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rstgen RST_UART0>;
status = "disabled";
};
};
--
2.25.1
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