[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20240110065757.xde2nvpr3z7c4isu@vireshk-i7>
Date: Wed, 10 Jan 2024 12:27:57 +0530
From: Viresh Kumar <viresh.kumar@...aro.org>
To: Krishna Chaitanya Chundru <quic_krichai@...cinc.com>
Cc: Bjorn Helgaas <helgaas@...nel.org>, agross@...nel.org,
andersson@...nel.org, konrad.dybcio@...aro.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
vireshk@...nel.org, nm@...com, sboyd@...nel.org, mani@...nel.org,
lpieralisi@...nel.org, kw@...ux.com, robh@...nel.org,
bhelgaas@...gle.com, rafael@...nel.org,
linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-pm@...r.kernel.org, quic_vbadigan@...cinc.com,
quic_nitegupt@...cinc.com, quic_skananth@...cinc.com,
quic_ramkri@...cinc.com, quic_parass@...cinc.com
Subject: Re: [PATCH v5 5/5] PCI: qcom: Add OPP support to scale performance
state of power domain
On 08-01-24, 18:49, Krishna Chaitanya Chundru wrote:
> We calculate ICC BW voting based up on PCIe speed and PCIe width.
>
> Right now we are adding the opp table based up on PCIe speed.
>
> Each PCIe controller can support multiple lane configurations like x1, x2,
> x4, x8, x16 based up on controller capability.
>
> So for each GEN speed we need up to 5 entries in OPP table. This will make
> OPP table very long.
>
> It is best to calculate the ICC BW voting in the driver itself and apply
> them through ICC driver.
I see. Are the lane configurations fixed for a platform ? I mean, do you change
those configurations at runtime or is that something that never changes, but the
driver can end up getting used on a hardware that supports any one of them ?
If they are fixed (second case), then you can use dev_pm_opp_set_prop_name() to
make that easier for you. With that you will only need 5 OPP entries, but each
of them will have five values of bw:
bw-x1, bw-x2, .... and you can select one of them during initialization.
--
viresh
Powered by blists - more mailing lists