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Date: Thu, 11 Jan 2024 14:50:37 +0000
From: patchwork-bot+linux-riscv@...nel.org
To: Samuel Holland <samuel.holland@...ive.com>
Cc: linux-riscv@...ts.infradead.org, aou@...s.berkeley.edu, conor@...nel.org,
krzysztof.kozlowski+dt@...aro.org, palmer@...belt.com,
paul.walmsley@...ive.com, robh+dt@...nel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] dt-bindings: riscv: cpus: Clarify mmu-type interpretation
Hello:
This patch was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@...osinc.com>:
On Wed, 27 Dec 2023 09:57:38 -0800 you wrote:
> The current description implies that only a single address translation
> mode is available to the operating system. However, some implementations
> support multiple address translation modes, and the operating system is
> free to choose between them.
>
> Per the RISC-V privileged specification, Sv48 implementations must also
> implement Sv39, and likewise Sv57 implies support for Sv48. This means
> it is possible to describe all supported address translation modes using
> a single value, by naming the largest supported mode. This appears to
> have been the intended usage of the property, so note it explicitly.
>
> [...]
Here is the summary with links:
- dt-bindings: riscv: cpus: Clarify mmu-type interpretation
https://git.kernel.org/riscv/c/b4070c2a242e
You are awesome, thank you!
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