Message-ID: <f4805d04-9514-6a41-b39e-aa8a4577ce90@quicinc.com>
Date: Fri, 12 Jan 2024 09:46:42 +0530
From: Krishna Chaitanya Chundru <quic_krichai@...cinc.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        Rob Herring
	<robh+dt@...nel.org>,
        Krzysztof Kozlowski
	<krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>
CC: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
        "Veerabhadrarao
 Badiganti" <quic_vbadigan@...cinc.com>,
        <quic_skananth@...cinc.com>, <bartosz.golaszewski@...aro.org>,
        open list <linux-kernel@...r.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
	<devicetree@...r.kernel.org>,
        "open list:PCIE ENDPOINT DRIVER FOR QUALCOMM"
	<linux-arm-msm@...r.kernel.org>,
        <p.zabel@...gutronix.de>, Bjorn Helgaas
	<bhelgaas@...gle.com>,
        "open list:PCIE ENDPOINT DRIVER FOR QUALCOMM"
	<linux-pci@...r.kernel.org>
Subject: Re: Proposal for QCOM PCIe switch power and configuration driver

++CC   Philipp Zabel ( reset controller maintainer)  & Bjorn & PCI list 
from PCIe subsytem.

On 1/11/2024 11:20 PM, Krzysztof Kozlowski wrote:
> On 11/01/2024 18:38, Krishna Chaitanya Chundru wrote:
>> Hi DT maintainers,
>>
>> We are trying to upstream the QCOM PCIe switch which has I2C interface
>> to configure the switch.
>>
>> In generic a PCIe switch is a device that allows expansion of PCI
>> Express hierarchy, which allows more devices(PCIe endpoints) to be
>> connected to a single PCIe port.
>>
>> We need to configure the QCOM switch like L0s, L1ss entry times, Tx
>> amplitudes etc.. through I2C interface before PCIe link is established
>> as these settings can affect link stability if we don't configure them.
>>
>> Once PCIe switch is configured, PCIe link between the PCIe switch and
>> PCIe port connected should be established by the QCOM PCIe controller
>> driver to enumerate the PCIe endpoints connected to the PCIe switch.
>>
>> We had a QCOM switch driver which powers on the switch and do the I2C
>> configurations.
>>
>> This is how the flow goes.
>> -->Power on the switch
>>       -->Do Switch configuration (over i2c) with qcom switch driver
>>           -->PCIe link training and enumeration.
> 
> And where is the PCI controller in this? Why isn't this represented like
> I2C or GPIO expander? You need to describe what exactly the switch is doing.
>
The PCIe link training and enumeration is handled by PCIe controller driver.
Usually a single endpoint will be connected to PCIe port, using a switch
we can connect multiple endpoints like WLAN, NVME, PCIe to ethernet
bridge etc. So in single instance of PCIe multiple endpoints are
connected and enumerated.
Like I2C or GPIO expander we don't want to configure any endpoints, here
we are trying to solve the initialization part of the switch power to
the switch and configuration of the switch before PCIe controller starts
link training and enumeration.

> Also, how about using existing solutions? Aren't there any? I am not
> going to look for them for you...
> 
As of I know we don't have any solutions exiting now, we are trying to
explore different ways for it.
> Anyway, you should ask (means Cc) reset controller maintainers if they
> are happy for such usage of reset framework for something not being a
> reset. For similar reasons you should Cc PCI maintainers. If you ask me,
> then no, PCI switch does not look like reset line so, you should not use
> reset lines.
> 
I added both maintainers now. sorry for the miss.
We want to use reset line because I2c driver has to power on the device
and configure the switch only before PCIe controller driver probes.
This is how reset controller operates(correct me if I was wrong).


Thanks & Regards,
Krishna Chaitanya.
> Best regards,
> Krzysztof
> 

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