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Message-ID: <9127808c-ab0c-83ce-9bc7-27f5daae30d1@quicinc.com>
Date: Tue, 16 Jan 2024 10:37:09 +0530
From: Krishna Chaitanya Chundru <quic_krichai@...cinc.com>
To: Bjorn Helgaas <helgaas@...nel.org>
CC: Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio
	<konrad.dybcio@...aro.org>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        "Lorenzo
 Pieralisi" <lpieralisi@...nel.org>,
        Krzysztof WilczyƄski
	<kw@...ux.com>,
        Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski
	<krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Manivannan Sadhasivam <mani@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Johan Hovold <johan+linaro@...nel.org>,
        Brian Masney <bmasney@...hat.com>, Georgi Djakov <djakov@...nel.org>,
        <linux-arm-msm@...r.kernel.org>, <vireshk@...nel.org>,
        <quic_vbadigan@...cinc.com>, <quic_skananth@...cinc.com>,
        <quic_nitegupt@...cinc.com>, <linux-pci@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v6 6/6] PCI: qcom: Add OPP support to scale performance
 state of power domain



On 1/12/2024 10:20 PM, Bjorn Helgaas wrote:
> On Fri, Jan 12, 2024 at 07:52:05PM +0530, Krishna chaitanya chundru wrote:
>> QCOM Resource Power Manager-hardened (RPMh) is a hardware block which
>> maintains hardware state of a regulator by performing max aggregation of
>> the requests made by all of the processors.
>>
>> PCIe controller can operate on different RPMh performance state of power
>> domain based up on the speed of the link. And this performance state varies
>> from target to target.
>>
>> It is manadate to scale the performance state based up on the PCIe speed
>> link operates so that SoC can run under optimum power conditions.
>>
>> Add Operating Performance Points(OPP) support to vote for RPMh state based
>> upon GEN speed link is operating.
> 
> Thanks for this "OPP" expansion!  Maybe "GEN" is unnecessary in this
> sentence?  And below, could be replaced with actual speeds?
> 
ACK
>> OPP can handle ICC bw voting also, so move icc bw voting through opp
>> framework if opp entries are present.
> 
> s/opp/OPP/ to match
> s/icc/ICC/ similarly (and perhaps expand once)
> Also below in comments, etc.
> 
ACK.

-Krishna Chaitanya.
>> In PCIe certain gen speeds like GEN1x2 & GEN2X1 or GEN3x2 & GEN4x1 use
>> same icc bw and has frequency, so use frequency based search to reduce
>> number of entries in the opp table.
>>
>> Don't initialize icc if opp is supported.
> 
> Bjorn

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