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Message-ID: <effe9e2c56baca76cbef09b0262c246478670bc2.camel@ew.tq-group.com>
Date: Tue, 23 Jan 2024 13:05:30 +0100
From: Matthias Schiffer <matthias.schiffer@...tq-group.com>
To: Christophe Leroy <christophe.leroy@...roup.eu>
Cc: Nicholas Piggin <npiggin@...il.com>, "Aneesh Kumar K.V"
<aneesh.kumar@...nel.org>, "Naveen N. Rao" <naveen.n.rao@...ux.ibm.com>,
"linuxppc-dev@...ts.ozlabs.org" <linuxppc-dev@...ts.ozlabs.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux@...tq-group.com" <linux@...tq-group.com>, Michael Ellerman
<mpe@...erman.id.au>
Subject: Re: [PATCH] powerpc/6xx: set High BAT Enable flag on G2 cores
On Fri, 2024-01-19 at 13:53 +0000, Christophe Leroy wrote:
>
> Le 19/01/2024 à 14:41, Matthias Schiffer a écrit :
> > >
> > > Thinking about it once more, can we do even more simple ?
> > >
> > > Why do we need that __setup_cpu_g2() at all ?
> > >
> > > You could just add the following into __set_cpu_603()
> > >
> > > diff --git a/arch/powerpc/kernel/cpu_setup_6xx.S
> > > b/arch/powerpc/kernel/cpu_setup_6xx.S
> > > index c67d32e04df9..7b41e3884866 100644
> > > --- a/arch/powerpc/kernel/cpu_setup_6xx.S
> > > +++ b/arch/powerpc/kernel/cpu_setup_6xx.S
> > > @@ -21,6 +21,11 @@ BEGIN_MMU_FTR_SECTION
> > > li r10,0
> > > mtspr SPRN_SPRG_603_LRU,r10 /* init SW LRU tracking */
> > > END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
> > > +BEGIN_MMU_FTR_SECTION
> > > + mfspr r11,SPRN_HID2_G2
> > > + oris r11,r11,HID2_HBE_G2@h
> > > + mtspr SPRN_HID2_G2,r11
> > > +END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
> > >
> > > BEGIN_FTR_SECTION
> > > bl __init_fpu_registers
> > > ---
> > >
> > > By the way, as your register is named SPRN_HID2_G2, the bit would better
> > > be named HID2_G2_HBE instead of HID2_HBE_G2 I think.
> >
> > My intention was to keep this consistent with the SPRN_HID2_GEKKO define.
>
> I don't understand what you mean. I can't see any bits defined for
> HID2_GEKKO.
>
> What I see which is simitar is the definition of TSC register for CELL CPU.
>
> #define SPRN_TSC_CELL 0x399 /* Thread switch control on Cell */
> #define TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */
> #define TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */
> #define TSC_CELL_EE_ENABLE 0x100000 /* External Interrupt */
> #define TSC_CELL_EE_BOOST 0x080000 /* External Interrupt Boost */
>
>
> They don't call it TSC_EE_BOOST_CELL or TSC_EE_ENABLE_CELL
Ah sorry, I got things mixed up. Will change the define to HID2_G2_HBE (or maybe HID_G2_LE_HBE?)
in v2.
Regards,
Matthias
>
>
> Christophe
>
> >
> > Regards,
> > Matthias
> >
> >
> >
> >
> > >
> > > Christophe
> > >
> > > >
> > > > >
> > > > > > +
> > > > > > +BEGIN_FTR_SECTION
> > > > > > + bl __init_fpu_registers
> > > > > > +END_FTR_SECTION_IFCLR(CPU_FTR_FPU_UNAVAILABLE)
> > > > > > + bl setup_common_caches
> > > > > > + bl setup_g2_hid2
> > > > > > + mtlr r5
> > > > > > + blr
> > > > > >
> > > > > > /* Enable caches for 603's, 604, 750 & 7400 */
> > > > > > SYM_FUNC_START_LOCAL(setup_common_caches)
> > > > > > @@ -115,6 +129,16 @@ SYM_FUNC_START_LOCAL(setup_604_hid0)
> > > > > > blr
> > > > > > SYM_FUNC_END(setup_604_hid0)
> > > > > >
> > > > > > +/* Enable high BATs for G2 (G2_LE, e300cX) */
> > > > > > +SYM_FUNC_START_LOCAL(setup_g2_hid2)
> > > > > > + mfspr r11,SPRN_HID2_G2
> > > > > > + oris r11,r11,HID2_HBE_G2@h
> > > > > > + mtspr SPRN_HID2_G2,r11
> > > > > > + sync
> > > > > > + isync
> > > > > > + blr
> > > > > > +SYM_FUNC_END(setup_g2_hid2)
> > > > > > +
> > > > > > /* 7400 <= rev 2.7 and 7410 rev = 1.0 suffer from some
> > > > > > * erratas we work around here.
> > > > > > * Moto MPC710CE.pdf describes them, those are errata
> > > > > > @@ -495,4 +519,3 @@ _GLOBAL(__restore_cpu_setup)
> > > > > > mtcr r7
> > > > > > blr
> > > > > > _ASM_NOKPROBE_SYMBOL(__restore_cpu_setup)
> > > > > > -
> > > > > > diff --git a/arch/powerpc/kernel/cpu_specs_book3s_32.h b/arch/powerpc/kernel/cpu_specs_book3s_32.h
> > > > > > index 3714634d194a1..83f054fcf837c 100644
> > > > > > --- a/arch/powerpc/kernel/cpu_specs_book3s_32.h
> > > > > > +++ b/arch/powerpc/kernel/cpu_specs_book3s_32.h
> > > > > > @@ -69,7 +69,7 @@ static struct cpu_spec cpu_specs[] __initdata = {
> > > > > > .mmu_features = MMU_FTR_USE_HIGH_BATS,
> > > > > > .icache_bsize = 32,
> > > > > > .dcache_bsize = 32,
> > > > > > - .cpu_setup = __setup_cpu_603,
> > > > > > + .cpu_setup = __setup_cpu_g2,
> > > > > > .machine_check = machine_check_generic,
> > > > > > .platform = "ppc603",
> > > > > > },
> > > > > > @@ -83,7 +83,7 @@ static struct cpu_spec cpu_specs[] __initdata = {
> > > > > > .mmu_features = MMU_FTR_USE_HIGH_BATS,
> > > > > > .icache_bsize = 32,
> > > > > > .dcache_bsize = 32,
> > > > > > - .cpu_setup = __setup_cpu_603,
> > > > > > + .cpu_setup = __setup_cpu_g2,
> > > > > > .machine_check = machine_check_83xx,
> > > > > > .platform = "ppc603",
> > > > > > },
> > > > > > @@ -96,7 +96,7 @@ static struct cpu_spec cpu_specs[] __initdata = {
> > > > > > .mmu_features = MMU_FTR_USE_HIGH_BATS | MMU_FTR_NEED_DTLB_SW_LRU,
> > > > > > .icache_bsize = 32,
> > > > > > .dcache_bsize = 32,
> > > > > > - .cpu_setup = __setup_cpu_603,
> > > > > > + .cpu_setup = __setup_cpu_g2,
> > > > > > .machine_check = machine_check_83xx,
> > > > > > .platform = "ppc603",
> > > > > > },
> > > > > > @@ -109,7 +109,7 @@ static struct cpu_spec cpu_specs[] __initdata = {
> > > > > > .mmu_features = MMU_FTR_USE_HIGH_BATS | MMU_FTR_NEED_DTLB_SW_LRU,
> > > > > > .icache_bsize = 32,
> > > > > > .dcache_bsize = 32,
> > > > > > - .cpu_setup = __setup_cpu_603,
> > > > > > + .cpu_setup = __setup_cpu_g2,
> > > > > > .machine_check = machine_check_83xx,
> > > > > > .num_pmcs = 4,
> > > > > > .platform = "ppc603",
> > > > > > @@ -123,7 +123,7 @@ static struct cpu_spec cpu_specs[] __initdata = {
> > > > > > .mmu_features = MMU_FTR_USE_HIGH_BATS | MMU_FTR_NEED_DTLB_SW_LRU,
> > > > > > .icache_bsize = 32,
> > > > > > .dcache_bsize = 32,
> > > > > > - .cpu_setup = __setup_cpu_603,
> > > > > > + .cpu_setup = __setup_cpu_g2,
> > > > > > .machine_check = machine_check_83xx,
> > > > > > .num_pmcs = 4,
> > > > > > .platform = "ppc603",
> > > > > > --
> > > > > > TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
> > > > > > Amtsgericht München, HRB 105018
> > > > > > Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
> > > > > > https://www.tq-group.com/
> > > >
> > > > --
> > > > TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
> > > > Amtsgericht München, HRB 105018
> > > > Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
> > > > https://www.tq-group.com/
> >
> > --
> > TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
> > Amtsgericht München, HRB 105018
> > Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
> > https://www.tq-group.com/
>
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
https://www.tq-group.com/
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