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Message-ID: <20240125165416.1987576-1-leyfoon.tan@starfivetech.com> Date: Fri, 26 Jan 2024 00:54:16 +0800 From: Ley Foon Tan <leyfoon.tan@...rfivetech.com> To: Daniel Lezcano <daniel.lezcano@...aro.org>, Thomas Gleixner <tglx@...utronix.de>, Palmer Dabbelt <palmer@...belt.com>, Paul Walmsley <paul.walmsley@...ive.com>, Albert Ou <aou@...s.berkeley.edu> Cc: atishp@...osinc.com, linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org, Ley Foon Tan <lftan.linux@...il.com> Subject: [PATCH] clocksource: timer-riscv: Clear timer interrupt on timer initialization In the RISC-V specification, the stimecmp register doesn't have a default value. To prevent the timer interrupt from being triggered during timer initialization, clear the timer interrupt by writing stimecmp with a maximum value. Signed-off-by: Ley Foon Tan <leyfoon.tan@...rfivetech.com> --- drivers/clocksource/timer-riscv.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index e66dcbd66566..a75a74647344 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -172,6 +172,9 @@ static int __init riscv_timer_init_common(void) sched_clock_register(riscv_sched_clock, 64, riscv_timebase); + /* Clear timer interrupt */ + riscv_clock_event_stop(); + error = request_percpu_irq(riscv_clock_event_irq, riscv_timer_interrupt, "riscv-timer", &riscv_clock_event); -- 2.43.0
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