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Message-ID: <55af5d4a-7bc9-4ae7-88c5-5acae4666450@sirena.org.uk>
Date: Thu, 25 Jan 2024 17:26:32 +0000
From: Mark Brown <broonie@...nel.org>
To: Tudor Ambarus <tudor.ambarus@...aro.org>
Cc: andi.shyti@...nel.org, arnd@...db.de, robh+dt@...nel.org,
	krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
	alim.akhtar@...sung.com, linux-spi@...r.kernel.org,
	linux-samsung-soc@...r.kernel.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	linux-arch@...r.kernel.org, andre.draszik@...aro.org,
	peter.griffin@...aro.org, semen.protsenko@...aro.org,
	kernel-team@...roid.com, willmcvicker@...gle.com
Subject: Re: [PATCH v2 05/28] spi: dt-bindings: samsung: add
 samsung,spi-fifosize property

On Thu, Jan 25, 2024 at 04:38:07PM +0000, Tudor Ambarus wrote:
> On 1/25/24 16:16, Mark Brown wrote:

> > Do we have any cases where we'd ever want to vary this independently of
> > the SoC - this isn't a configurable IP shipped to random integrators?

> The IP supports FIFO depths from 8 to 256 bytes (in powers of 2 I
> guess). The integrator is the one dictating the IP configuration. In
> gs101's case all USIxx_USI (which includes SPI, I2C, and UART) are
> configured with 64 bytes FIFO depths.

OK, so just the compatible is enough information then?

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