[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20240125062739.1339782-3-debug@rivosinc.com>
Date: Wed, 24 Jan 2024 22:21:27 -0800
From: debug@...osinc.com
To: rick.p.edgecombe@...el.com,
broonie@...nel.org,
Szabolcs.Nagy@....com,
kito.cheng@...ive.com,
keescook@...omium.org,
ajones@...tanamicro.com,
paul.walmsley@...ive.com,
palmer@...belt.com,
conor.dooley@...rochip.com,
cleger@...osinc.com,
atishp@...shpatra.org,
alex@...ti.fr,
bjorn@...osinc.com,
alexghiti@...osinc.com
Cc: corbet@....net,
aou@...s.berkeley.edu,
oleg@...hat.com,
akpm@...ux-foundation.org,
arnd@...db.de,
ebiederm@...ssion.com,
shuah@...nel.org,
brauner@...nel.org,
debug@...osinc.com,
guoren@...nel.org,
samitolvanen@...gle.com,
evan@...osinc.com,
xiao.w.wang@...el.com,
apatel@...tanamicro.com,
mchitale@...tanamicro.com,
waylingii@...il.com,
greentime.hu@...ive.com,
heiko@...ech.de,
jszhang@...nel.org,
shikemeng@...weicloud.com,
david@...hat.com,
charlie@...osinc.com,
panqinglin2020@...as.ac.cn,
willy@...radead.org,
vincent.chen@...ive.com,
andy.chiu@...ive.com,
gerg@...nel.org,
jeeheng.sia@...rfivetech.com,
mason.huo@...rfivetech.com,
ancientmodern4@...il.com,
mathis.salmen@...sal.de,
cuiyunhui@...edance.com,
bhe@...hat.com,
chenjiahao16@...wei.com,
ruscur@...sell.cc,
bgray@...ux.ibm.com,
alx@...nel.org,
baruch@...s.co.il,
zhangqing@...ngson.cn,
catalin.marinas@....com,
revest@...omium.org,
josh@...htriplett.org,
joey.gouly@....com,
shr@...kernel.io,
omosnace@...hat.com,
ojeda@...nel.org,
jhubbard@...dia.com,
linux-doc@...r.kernel.org,
linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org,
linux-mm@...ck.org,
linux-arch@...r.kernel.org,
linux-kselftest@...r.kernel.org
Subject: [RFC PATCH v1 02/28] riscv: envcfg save and restore on trap entry/exit
From: Deepak Gupta <debug@...osinc.com>
envcfg CSR defines enabling bits for cache management instructions and soon
will control enabling for control flow integrity and pointer masking features.
Control flow integrity enabling for forward cfi and backward cfi is controlled
via envcfg and thus need to be enabled on per thread basis.
This patch creates a place holder for envcfg CSR in `thread_info` and adds
logic to save and restore on trap entry and exits.
Signed-off-by: Deepak Gupta <debug@...osinc.com>
---
arch/riscv/include/asm/thread_info.h | 1 +
arch/riscv/kernel/asm-offsets.c | 1 +
arch/riscv/kernel/entry.S | 4 ++++
3 files changed, 6 insertions(+)
diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/thread_info.h
index 574779900bfb..320bc899a63b 100644
--- a/arch/riscv/include/asm/thread_info.h
+++ b/arch/riscv/include/asm/thread_info.h
@@ -57,6 +57,7 @@ struct thread_info {
long user_sp; /* User stack pointer */
int cpu;
unsigned long syscall_work; /* SYSCALL_WORK_ flags */
+ unsigned long envcfg;
#ifdef CONFIG_SHADOW_CALL_STACK
void *scs_base;
void *scs_sp;
diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c
index a03129f40c46..cdd8f095c30c 100644
--- a/arch/riscv/kernel/asm-offsets.c
+++ b/arch/riscv/kernel/asm-offsets.c
@@ -39,6 +39,7 @@ void asm_offsets(void)
OFFSET(TASK_TI_PREEMPT_COUNT, task_struct, thread_info.preempt_count);
OFFSET(TASK_TI_KERNEL_SP, task_struct, thread_info.kernel_sp);
OFFSET(TASK_TI_USER_SP, task_struct, thread_info.user_sp);
+ OFFSET(TASK_TI_ENVCFG, task_struct, thread_info.envcfg);
#ifdef CONFIG_SHADOW_CALL_STACK
OFFSET(TASK_TI_SCS_SP, task_struct, thread_info.scs_sp);
#endif
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 54ca4564a926..63c3855ba80d 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -129,6 +129,10 @@ SYM_CODE_START_NOALIGN(ret_from_exception)
addi s0, sp, PT_SIZE_ON_STACK
REG_S s0, TASK_TI_KERNEL_SP(tp)
+ /* restore envcfg bits for current thread */
+ REG_L s0, TASK_TI_ENVCFG(tp)
+ csrw CSR_ENVCFG, s0
+
/* Save the kernel shadow call stack pointer */
scs_save_current
--
2.43.0
Powered by blists - more mailing lists