[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20240125062739.1339782-4-debug@rivosinc.com>
Date: Wed, 24 Jan 2024 22:21:28 -0800
From: debug@...osinc.com
To: rick.p.edgecombe@...el.com,
broonie@...nel.org,
Szabolcs.Nagy@....com,
kito.cheng@...ive.com,
keescook@...omium.org,
ajones@...tanamicro.com,
paul.walmsley@...ive.com,
palmer@...belt.com,
conor.dooley@...rochip.com,
cleger@...osinc.com,
atishp@...shpatra.org,
alex@...ti.fr,
bjorn@...osinc.com,
alexghiti@...osinc.com
Cc: corbet@....net,
aou@...s.berkeley.edu,
oleg@...hat.com,
akpm@...ux-foundation.org,
arnd@...db.de,
ebiederm@...ssion.com,
shuah@...nel.org,
brauner@...nel.org,
debug@...osinc.com,
guoren@...nel.org,
samitolvanen@...gle.com,
evan@...osinc.com,
xiao.w.wang@...el.com,
apatel@...tanamicro.com,
mchitale@...tanamicro.com,
waylingii@...il.com,
greentime.hu@...ive.com,
heiko@...ech.de,
jszhang@...nel.org,
shikemeng@...weicloud.com,
david@...hat.com,
charlie@...osinc.com,
panqinglin2020@...as.ac.cn,
willy@...radead.org,
vincent.chen@...ive.com,
andy.chiu@...ive.com,
gerg@...nel.org,
jeeheng.sia@...rfivetech.com,
mason.huo@...rfivetech.com,
ancientmodern4@...il.com,
mathis.salmen@...sal.de,
cuiyunhui@...edance.com,
bhe@...hat.com,
chenjiahao16@...wei.com,
ruscur@...sell.cc,
bgray@...ux.ibm.com,
alx@...nel.org,
baruch@...s.co.il,
zhangqing@...ngson.cn,
catalin.marinas@....com,
revest@...omium.org,
josh@...htriplett.org,
joey.gouly@....com,
shr@...kernel.io,
omosnace@...hat.com,
ojeda@...nel.org,
jhubbard@...dia.com,
linux-doc@...r.kernel.org,
linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org,
linux-mm@...ck.org,
linux-arch@...r.kernel.org,
linux-kselftest@...r.kernel.org
Subject: [RFC PATCH v1 03/28] riscv: define default value for envcfg
From: Deepak Gupta <debug@...osinc.com>
Defines a base default value for envcfg per task. By default all tasks
should have cache zeroing capability. Any future capabilities can be
turned on.
Signed-off-by: Deepak Gupta <debug@...osinc.com>
---
arch/riscv/include/asm/csr.h | 2 ++
arch/riscv/kernel/process.c | 1 +
2 files changed, 3 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index b3400517b0a9..01ba87954da2 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -202,6 +202,8 @@
#define ENVCFG_CBIE_FLUSH _AC(0x1, UL)
#define ENVCFG_CBIE_INV _AC(0x3, UL)
#define ENVCFG_FIOM _AC(0x1, UL)
+/* by default all threads should be able to zero cache */
+#define ENVCFG_BASE ENVCFG_CBZE
/* Smstateen bits */
#define SMSTATEEN0_AIA_IMSIC_SHIFT 58
diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c
index 4f21d970a129..2420123444c4 100644
--- a/arch/riscv/kernel/process.c
+++ b/arch/riscv/kernel/process.c
@@ -152,6 +152,7 @@ void start_thread(struct pt_regs *regs, unsigned long pc,
else
regs->status |= SR_UXL_64;
#endif
+ current->thread_info.envcfg = ENVCFG_BASE;
}
void flush_thread(void)
--
2.43.0
Powered by blists - more mailing lists