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Date: Thu, 25 Jan 2024 14:41:18 +0100
From: neil.armstrong@...aro.org
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
 Bjorn Andersson <andersson@...nel.org>,
 Konrad Dybcio <konrad.dybcio@...aro.org>, Rob Herring <robh+dt@...nel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
 Conor Dooley <conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 5/6] arm64: dts: qcom: sm8550: describe all PCI MSI
 interrupts

On 25/01/2024 14:06, Krzysztof Kozlowski wrote:
> Each group of MSI interrupts is mapped to the separate host interrupt.
> Describe each of interrupts in the device tree for PCIe hosts.  Only
> boot tested on hardware.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> ---
>   arch/arm64/boot/dts/qcom/sm8550.dtsi | 24 ++++++++++++++++++++----
>   1 file changed, 20 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index ee1ba5a8c8fc..80e31fb21055 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -1713,8 +1713,16 @@ pcie0: pcie@...0000 {
>   			linux,pci-domain = <0>;
>   			num-lanes = <2>;
>   
> -			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
> -			interrupt-names = "msi";
> +			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "msi0", "msi1", "msi2", "msi3",
> +					  "msi4", "msi5", "msi6", "msi7";
>   
>   			#interrupt-cells = <1>;
>   			interrupt-map-mask = <0 0 0 0x7>;
> @@ -1804,8 +1812,16 @@ pcie1: pcie@...8000 {
>   			linux,pci-domain = <1>;
>   			num-lanes = <2>;
>   
> -			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
> -			interrupt-names = "msi";
> +			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "msi0", "msi1", "msi2", "msi3",
> +					  "msi4", "msi5", "msi6", "msi7";
>   
>   			#interrupt-cells = <1>;
>   			interrupt-map-mask = <0 0 0 0x7>;

230:         22          0          0          0          0          0          0          0   PCI-MSI 134742016 Edge      nvme0q0
232:          0          0          0          0          0          0          0          0   PCI-MSI 134742017 Edge      nvme0q1
233:          1          0          0          0          0          0          0          0   PCI-MSI 134742018 Edge      nvme0q2
234:          0          0          0          0          0          0          0          0   PCI-MSI 134742019 Edge      nvme0q3
235:          1          0          0          0          0          0          0          0   PCI-MSI 134742020 Edge      nvme0q4
236:          1          0          0          0          0          0          0          0   PCI-MSI 134742021 Edge      nvme0q5
237:         23          0          0          0          0          0          0          0   PCI-MSI 134742022 Edge      nvme0q6
238:         18          0          0          0          0          0          0          0   PCI-MSI 134742023 Edge      nvme0q7
239:          0          0          0          0          0          0          0          0   PCI-MSI 134742024 Edge      nvme0q8
258:          4          0          0          0          0          0          0          0   PCI-MSI 524288 Edge      bhi
259:          5          0          0          0          0          0          0          0   PCI-MSI 524289 Edge      mhi
260:         33          0          0          0          0          0          0          0   PCI-MSI 524290 Edge      mhi
261:          3          0          0          0          0          0          0          0   PCI-MSI 524291 Edge      ce0
262:          2          0          0          0          0          0          0          0   PCI-MSI 524292 Edge      ce1
263:         41          0          0          0          0          0          0          0   PCI-MSI 524293 Edge      ce2
264:         28          0          0          0          0          0          0          0   PCI-MSI 524294 Edge      ce3
265:          0          0          0          0          0          0          0          0   PCI-MSI 524295 Edge      ce5
266:          0          0          0          0          0          0          0          0   PCI-MSI 524296 Edge      DP_EXT_IRQ
267:          0          0          0          0          0          0          0          0   PCI-MSI 524297 Edge      DP_EXT_IRQ
268:          0          0          0          0          0          0          0          0   PCI-MSI 524298 Edge      DP_EXT_IRQ
269:          0          0          0          0          0          0          0          0   PCI-MSI 524299 Edge      DP_EXT_IRQ
270:          0          0          0          0          0          0          0          0   PCI-MSI 524300 Edge      DP_EXT_IRQ
271:          0          0          0          0          0          0          0          0   PCI-MSI 524301 Edge      DP_EXT_IRQ
272:          0          0          0          0          0          0          0          0   PCI-MSI 524302 Edge      DP_EXT_IRQ

Tested-by: Neil Armstrong <neil.armstrong@...aro.org> # on SM8550-HDK

235:          4          0          0          0          0          0          0          0   PCI-MSI 524288 Edge      bhi
236:          5          0          0          0          0          0          0          0   PCI-MSI 524289 Edge      mhi
237:         33          0          0          0          0          0          0          0   PCI-MSI 524290 Edge      mhi
238:          3          0          0          0          0          0          0          0   PCI-MSI 524291 Edge      ce0
239:          2          0          0          0          0          0          0          0   PCI-MSI 524292 Edge      ce1
240:         40          0          0          0          0          0          0          0   PCI-MSI 524293 Edge      ce2
241:         29          0          0          0          0          0          0          0   PCI-MSI 524294 Edge      ce3
242:          0          0          0          0          0          0          0          0   PCI-MSI 524295 Edge      ce5
243:          0          0          0          0          0          0          0          0   PCI-MSI 524296 Edge      DP_EXT_IRQ
244:          0          0          0          0          0          0          0          0   PCI-MSI 524297 Edge      DP_EXT_IRQ
245:          0          0          0          0          0          0          0          0   PCI-MSI 524298 Edge      DP_EXT_IRQ
246:          0          0          0          0          0          0          0          0   PCI-MSI 524299 Edge      DP_EXT_IRQ
247:          0          0          0          0          0          0          0          0   PCI-MSI 524300 Edge      DP_EXT_IRQ
248:          0          0          0          0          0          0          0          0   PCI-MSI 524301 Edge      DP_EXT_IRQ
249:          0          0          0          0          0          0          0          0   PCI-MSI 524302 Edge      DP_EXT_IRQ


Tested-by: Neil Armstrong <neil.armstrong@...aro.org> # on SM8550-QRD

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