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Message-ID: <59ea1ace-7505-4275-bcfa-766e25e621b4@linaro.org>
Date: Thu, 25 Jan 2024 14:43:02 +0100
From: neil.armstrong@...aro.org
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 6/6] arm64: dts: qcom: sm8650: describe all PCI MSI
interrupts
On 25/01/2024 14:06, Krzysztof Kozlowski wrote:
> Each group of MSI interrupts is mapped to the separate host interrupt.
> Describe each of interrupts in the device tree for PCIe hosts. Not
> tested on hardware.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8650.dtsi | 24 ++++++++++++++++++++----
> 1 file changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> index 2df77123a8c7..9fc4f3e37a8c 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> @@ -2213,8 +2213,16 @@ pcie0: pci@...0000 {
> <0 0x60100000 0 0x100000>;
> reg-names = "parf", "dbi", "elbi", "atu", "config";
>
> - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "msi";
> + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi0", "msi1", "msi2", "msi3",
> + "msi4", "msi5", "msi6", "msi7";
>
> clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
> <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> @@ -2317,8 +2325,16 @@ pcie1: pci@...8000 {
> "atu",
> "config";
>
> - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "msi";
> + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi0", "msi1", "msi2", "msi3",
> + "msi4", "msi5", "msi6", "msi7";
>
> clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
> <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
175: 4 0 0 0 0 0 0 0 PCI-MSI 524288 Edge bhi
176: 5 0 0 0 0 0 0 0 PCI-MSI 524289 Edge mhi
177: 34 0 0 0 0 0 0 0 PCI-MSI 524290 Edge mhi
178: 3 0 0 0 0 0 0 0 PCI-MSI 524291 Edge ce0
179: 2 0 0 0 0 0 0 0 PCI-MSI 524292 Edge ce1
180: 42 0 0 0 0 0 0 0 PCI-MSI 524293 Edge ce2
181: 29 0 0 0 0 0 0 0 PCI-MSI 524294 Edge ce3
182: 0 0 0 0 0 0 0 0 PCI-MSI 524295 Edge ce5
183: 0 0 0 0 0 0 0 0 PCI-MSI 524296 Edge DP_EXT_IRQ
184: 0 0 0 0 0 0 0 0 PCI-MSI 524297 Edge DP_EXT_IRQ
185: 0 0 0 0 0 0 0 0 PCI-MSI 524298 Edge DP_EXT_IRQ
186: 0 0 0 0 0 0 0 0 PCI-MSI 524299 Edge DP_EXT_IRQ
187: 0 0 0 0 0 0 0 0 PCI-MSI 524300 Edge DP_EXT_IRQ
188: 0 0 0 0 0 0 0 0 PCI-MSI 524301 Edge DP_EXT_IRQ
189: 0 0 0 0 0 0 0 0 PCI-MSI 524302 Edge DP_EXT_IRQ
Tested-by: Neil Armstrong <neil.armstrong@...aro.org> # on SM8650-QRD
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