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Message-ID: <85dd3df3-9c0e-45e2-af8d-50dbc0cf40c8@intel.com>
Date: Wed, 31 Jan 2024 07:33:36 -0800
From: Dave Hansen <dave.hansen@...el.com>
To: Tony W Wang-oc <TonyWWang-oc@...oxin.com>, herbert@...dor.apana.org.au,
 davem@...emloft.net, linux-crypto@...r.kernel.org,
 linux-kernel@...r.kernel.org, tglx@...utronix.de, mingo@...hat.com,
 bp@...en8.de, dave.hansen@...ux.intel.com, x86@...nel.org, hpa@...or.com,
 seanjc@...gle.com, kim.phillips@....com, kirill.shutemov@...ux.intel.com,
 jmattson@...gle.com, babu.moger@....com, kai.huang@...el.com,
 acme@...hat.com, aik@....com, namhyung@...nel.org
Cc: CobeChen@...oxin.com, TimGuo@...oxin.com, LeoLiu-oc@...oxin.com,
 GeorgeXue@...oxin.com
Subject: Re: [PATCH v2 1/3] crypto: padlock-sha: Matches CPU with Family with
 6 explicitly

On 1/31/24 01:45, Tony W Wang-oc wrote:
>>>   static const struct x86_cpu_id padlock_sha_ids[] = {
>>> -     X86_MATCH_FEATURE(X86_FEATURE_PHE, NULL),
>>> +     X86_MATCH_VENDOR_FAM_FEATURE(CENTAUR, 6, X86_FEATURE_PHE, NULL),
>>>        {}
>>>   };
>> Logically, this is saying that there are non-CENTAUR or non-family-6
>> CPUs that set X86_FEATURE_PHE, but don't support X86_FEATURE_PHE.  Is
>> that the case?
> 
> Not exactly.
> 
> Zhaoxin CPU supports X86_FEATURE_PHE and X86_FEATURE_PHE2.
> 
> We expect the Zhaoxin CPU to use the zhaoxin_sha driver introduced in
> the third patch of this patch set.
> 
> Without this patch Zhaoxin CPU will also match the padlock-sha driver too.

I honestly have no idea what this is saying.

Could you try again, please?

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