Message-Id: <1036060c-25dd-439b-b081-893d0cb000f6@app.fastmail.com>
Date: Wed, 31 Jan 2024 11:28:57 +0100
From: "Arnd Bergmann" <arnd@...db.de>
To: "Yann Sionneau" <ysionneau@...rayinc.com>,
 "Krzysztof Kozlowski" <krzysztof.kozlowski@...aro.org>,
 "Yann Sionneau" <ysionneau@...ray.eu>,
 "Jonathan Corbet" <corbet@....net>,
 "Thomas Gleixner" <tglx@...utronix.de>, "Marc Zyngier" <maz@...nel.org>,
 "Rob Herring" <robh+dt@...nel.org>,
 "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@...aro.org>,
 "Will Deacon" <will@...nel.org>, "Peter Zijlstra" <peterz@...radead.org>,
 "Boqun Feng" <boqun.feng@...il.com>,
 "Mark Rutland" <mark.rutland@....com>,
 "Eric W. Biederman" <ebiederm@...ssion.com>,
 "Kees Cook" <keescook@...omium.org>, "Oleg Nesterov" <oleg@...hat.com>,
 "Ingo Molnar" <mingo@...hat.com>, "Waiman Long" <longman@...hat.com>,
 "Aneesh Kumar" <aneesh.kumar@...ux.ibm.com>,
 "Andrew Morton" <akpm@...ux-foundation.org>,
 "Nicholas Piggin" <npiggin@...il.com>,
 "Paul Moore" <paul@...l-moore.com>, "Eric Paris" <eparis@...hat.com>,
 "Christian Brauner" <brauner@...nel.org>,
 "Paul Walmsley" <paul.walmsley@...ive.com>,
 "Palmer Dabbelt" <palmer@...belt.com>,
 "Albert Ou" <aou@...s.berkeley.edu>,
 "Jules Maselbas" <jmaselbas@...ray.eu>,
 "Guillaume Thouvenin" <gthouvenin@...ray.eu>,
 "Clement Leger" <clement@...ment-leger.fr>,
 "Vincent Chardon" <vincent.chardon@...ys-design.com>,
 Marc Poulhiès <dkm@...aplop.net>,
 "Julian Vetter" <jvetter@...ray.eu>, "Samuel Jones" <sjones@...ray.eu>,
 "Ashley Lesdalons" <alesdalons@...ray.eu>,
 "Thomas Costis" <tcostis@...ray.eu>, "Marius Gligor" <mgligor@...ray.eu>,
 "Jonathan Borne" <jborne@...ray.eu>,
 "Julien Villette" <jvillette@...ray.eu>,
 "Luc Michel" <lmichel@...ray.eu>, "Louis Morhet" <lmorhet@...ray.eu>,
 "Julien Hascoet" <jhascoet@...ray.eu>,
 "Jean-Christophe Pince" <jcpince@...il.com>,
 "Guillaume Missonnier" <gmissonnier@...ray.eu>,
 "Alex Michon" <amichon@...ray.eu>, "Huacai Chen" <chenhuacai@...nel.org>,
 "WANG Xuerui" <git@...0n.name>,
 "Shaokun Zhang" <zhangshaokun@...ilicon.com>,
 "John Garry" <john.garry@...wei.com>,
 "Guangbin Huang" <huangguangbin2@...wei.com>,
 "Bharat Bhushan" <bbhushan2@...vell.com>,
 "Bibo Mao" <maobibo@...ngson.cn>, "Atish Patra" <atishp@...shpatra.org>,
 "Jason A . Donenfeld" <Jason@...c4.com>, "Qi Liu" <liuqi115@...wei.com>,
 "Jiaxun Yang" <jiaxun.yang@...goat.com>,
 "Catalin Marinas" <catalin.marinas@....com>,
 "Mark Brown" <broonie@...nel.org>,
 "Janosch Frank" <frankja@...ux.ibm.com>,
 "Alexey Dobriyan" <adobriyan@...il.com>,
 "Julian Vetter" <jvetter@...rayinc.com>, jmaselbas@...v.net
Cc: "Benjamin Mugnier" <mugnier.benjamin@...il.com>,
 linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org,
 devicetree@...r.kernel.org, linux-mm@...ck.org,
 Linux-Arch <linux-arch@...r.kernel.org>, linux-audit@...hat.com,
 linux-riscv@...ts.infradead.org, bpf@...r.kernel.org
Subject: Re: [RFC PATCH v2 31/31] kvx: Add IPI driver

On Wed, Jan 31, 2024, at 10:52, Yann Sionneau wrote:
> On 22/01/2023 12:54, Krzysztof Kozlowski wrote:
>> On 20/01/2023 15:10, Yann Sionneau wrote:
>>> +
>>> +int __init kvx_ipi_ctrl_probe(irqreturn_t (*ipi_irq_handler)(int, void *))
>>> +{
>>> +	struct device_node *np;
>>> +	int ret;
>>> +	unsigned int ipi_irq;
>>> +	void __iomem *ipi_base;
>>> +
>>> +	np = of_find_compatible_node(NULL, NULL, "kalray,kvx-ipi-ctrl");
>> Nope, big no.
>>
>> Drivers go to drivers, not to arch code. Use proper driver infrastructure.
> Thank you for your review.
>
> It raises questions on our side about how to handle this change.
>
> First let me describe the hardware:
>
> The coolidge ipi controller device handles IPI communication between cpus
> inside a cluster.
>
> Each cpu has 8 of its dedicated irq lines (24 to 31) hard-wired to the ipi.
> The ipi controller has 8 sets of 2 registers:
> - a 17-bit "interrupt" register
> - a 17-bit "mask" register
>
> Each couple of register is dedicated to 1 of the 8 irqlines.
> Each of the 17 bits of interrupt/mask register
> identifies a cpu (cores 0 to 15 + secure_core).
> Writing bit i in interrupt register sends an irq to cpu i, according to the mask
> in mask register.
> Writing in interrupt/mask register couple N targets irq line N of the core.
>
> - Ipi generates an interrupt to the cpu when message is ready.
> - Messages are delivered via Axi.
> - Ipi does not have any interrupt input lines.
>
>
>   +---------------+   irq       axi_w
>   |         |  i  |<--/--- ipi <------
>   | CPU     |  n  |  x8
>   |  core0  |  t  |
>   |         |  c  |  irq          irq         msi
>   |         |  t  |<--/--- apic <----- mbox <-------
>   |         |  l  |  x4
>   +---------------+
>   with intctl = core-irq controller
>    
>
> We analyzed how other Linux ports are handling this situation (IPI) and 
> here are several possible solutions:
>
> 1/ put everything in smp.c like what longarch is doing.
>   * Except that IPI in longarch seems to involve writing to a special 
> purpose CPU register and not doing a memory mapped write like kvx.
>
> 2/ write a device driver in drivers/xxx/ with the content from ipi.c
>   * the probe would just ioremap the reg from DT and register the irq 
> using request_percpu_irq()
>   * it would export a function "kvx_ipi_send()" that would directly be 
> called by smp.c
>   * Question : where would this driver be placed in drivers/ ? 
> drivers/irqchip/ ? Even if this is not per-se an interrupt-controller 
> driver?

This looks like it's close enough to the irqchip driver
that you can just have it in the same file as the 'intctl'
portion.

Top-level irqchip implementations tend to be rather architecture
specific, as does the IPI mechanism. Depending on the register
layout, I think you can have a single devicetree node for
the combination of the core-irq (for managing your
own interrupts) and the ipi (for receiving interrupts from
others), and then have a driver in drivers/irqchip to
deal with both. For the ipi mechanism, trying to abstract
it too much generally makes it too slow, so I would not
go through a nested irqchip or a mailbox driver etc.

I don't know what the 'apic' in your diagram is, so that
would be either a nested irqchip or could be part of
the same driver as well.

     Arnd

Powered by blists - more mailing lists