| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Sun, 11 Feb 2024 20:24:36 +0100
From: Johan Jonker <jbx6244@...dex.com>
To: Sebastian Reichel <sebastian.reichel@...labora.com>,
Heiko Stuebner <heiko@...ech.de>, Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
linux-rockchip@...ts.infradead.org, linux-phy@...ts.infradead.org
Cc: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>, Frank Wang <frank.wang@...k-chips.com>,
Kever Yang <kever.yang@...k-chips.com>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, kernel@...labora.com
Subject: Re: [PATCH v1 06/10] arm64: dts: rockchip: add USBDP phys on rk3588
On 2/9/24 19:17, Sebastian Reichel wrote:
> Add both USB3-Displayport PHYs to RK3588 SoC DT.
>
> Signed-off-by: Sebastian Reichel <sebastian.reichel@...labora.com>
> ---
> arch/arm64/boot/dts/rockchip/rk3588.dtsi | 62 +++++++++++++++++++
> arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 73 +++++++++++++++++++++++
> 2 files changed, 135 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> index 5519c1430cb7..c26288ec75ce 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> @@ -17,6 +17,37 @@ pipe_phy1_grf: syscon@...c0000 {
> reg = <0x0 0xfd5c0000 0x0 0x100>;
> };
>
> + usbdpphy1_grf: syscon@...cc000 {
> + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
> + reg = <0x0 0xfd5cc000 0x0 0x4000>;
> + };
> +
> + usb2phy1_grf: syscon@...d4000 {
> + compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
> + "simple-mfd";
Use same line like usb2phy2_grf.
> + reg = <0x0 0xfd5d4000 0x0 0x4000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + u2phy1: usb2-phy@...0 {
"usb2phy@[0-9a-f]+$":
> + compatible = "rockchip,rk3588-usb2phy";
> + reg = <0x4000 0x10>;
> + interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
> + resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
> + reset-names = "phy", "apb";
> + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
> + clock-names = "phyclk";
> + clock-output-names = "usb480m_phy1";
> + #clock-cells = <0>;
Align with the (new) documentation
about property ordering.
> + status = "disabled";
> +
> + u2phy1_otg: otg-port {
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> + };
> + };
> +
> i2s8_8ch: i2s@...c8000 {
> compatible = "rockchip,rk3588-i2s-tdm";
> reg = <0x0 0xfddc8000 0x0 0x1000>;
> @@ -310,6 +341,37 @@ sata-port@0 {
> };
> };
>
> + usbdp_phy1: phy@...90000 {
> + compatible = "rockchip,rk3588-usbdp-phy";
> + reg = <0x0 0xfed90000 0x0 0x10000>;
> + rockchip,u2phy-grf = <&usb2phy1_grf>;
> + rockchip,usb-grf = <&usb_grf>;
> + rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
> + rockchip,vo-grf = <&vo0_grf>;
> + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
> + <&cru CLK_USBDP_PHY1_IMMORTAL>,
> + <&cru PCLK_USBDPPHY1>,
> + <&u2phy1>;
> + clock-names = "refclk", "immortal", "pclk", "utmi";
> + resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
> + <&cru SRST_USBDP_COMBO_PHY1_CMN>,
> + <&cru SRST_USBDP_COMBO_PHY1_LANE>,
> + <&cru SRST_USBDP_COMBO_PHY1_PCS>,
> + <&cru SRST_P_USBDPPHY1>;
> + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
Align with the (new) documentation
about property ordering.
> + status = "disabled";
> +
> + usbdp_phy1_dp: dp-port {
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> +
> + usbdp_phy1_u3: usb3-port {
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> + };
> +
> combphy1_ps: phy@...10000 {
> compatible = "rockchip,rk3588-naneng-combphy";
> reg = <0x0 0xfee10000 0x0 0x100>;
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> index 36b1b7acfe6a..553e1883cfe4 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> @@ -536,6 +536,37 @@ pipe_phy2_grf: syscon@...c4000 {
> reg = <0x0 0xfd5c4000 0x0 0x100>;
> };
>
> + usbdpphy0_grf: syscon@...c8000 {
> + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
> + reg = <0x0 0xfd5c8000 0x0 0x4000>;
> + };
> +
> + usb2phy0_grf: syscon@...d0000 {
> + compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
> + "simple-mfd";
Use same line like usb2phy2_grf.
> + reg = <0x0 0xfd5d0000 0x0 0x4000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + u2phy0: usb2-phy@0 {
>From grf.yaml:
"usb2phy@[0-9a-f]+$":
> + compatible = "rockchip,rk3588-usb2phy";
> + reg = <0x0 0x10>;
> + interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
> + resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
> + reset-names = "phy", "apb";
> + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
> + clock-names = "phyclk";
> + clock-output-names = "usb480m_phy0";
> + #clock-cells = <0>;
Align with the (new) documentation
about property ordering.
> + status = "disabled";
> +
> + u2phy0_otg: otg-port {
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> + };
> + };
> +
> usb2phy2_grf: syscon@...d8000 {
> compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
Fix usb2phy2_grf as well.
"usb2phy@[0-9a-f]+$":
> reg = <0x0 0xfd5d8000 0x0 0x4000>;
> @@ -561,6 +592,17 @@ u2phy2_host: host-port {
> };
> };
>
> + vo0_grf: syscon@...a6000 {
> + compatible = "rockchip,rk3588-vo-grf", "syscon";
> + reg = <0x0 0xfd5a6000 0x0 0x2000>;
> + clocks = <&cru PCLK_VO0GRF>;
> + };
> +
> + usb_grf: syscon@...ac000 {
> + compatible = "rockchip,rk3588-usb-grf", "syscon";
> + reg = <0x0 0xfd5ac000 0x0 0x4000>;
> + };
> +
> usb2phy3_grf: syscon@...dc000 {
> compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
Fix usb2phy3_grf as well.
"usb2phy@[0-9a-f]+$":
> reg = <0x0 0xfd5dc000 0x0 0x4000>;
> @@ -2360,6 +2402,37 @@ dmac2: dma-controller@...10000 {
> #dma-cells = <1>;
> };
>
> + usbdp_phy0: phy@...80000 {
> + compatible = "rockchip,rk3588-usbdp-phy";
> + reg = <0x0 0xfed80000 0x0 0x10000>;
> + rockchip,u2phy-grf = <&usb2phy0_grf>;
> + rockchip,usb-grf = <&usb_grf>;
> + rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
> + rockchip,vo-grf = <&vo0_grf>;
> + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
> + <&cru CLK_USBDP_PHY0_IMMORTAL>,
> + <&cru PCLK_USBDPPHY0>,
> + <&u2phy0>;
> + clock-names = "refclk", "immortal", "pclk", "utmi";
> + resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
> + <&cru SRST_USBDP_COMBO_PHY0_CMN>,
> + <&cru SRST_USBDP_COMBO_PHY0_LANE>,
> + <&cru SRST_USBDP_COMBO_PHY0_PCS>,
> + <&cru SRST_P_USBDPPHY0>;
> + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
Align with the (new) documentation
about property ordering.
> + status = "disabled";
> +
> + usbdp_phy0_dp: dp-port {
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> +
> + usbdp_phy0_u3: usb3-port {
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> + };
> +
> combphy0_ps: phy@...00000 {
> compatible = "rockchip,rk3588-naneng-combphy";
> reg = <0x0 0xfee00000 0x0 0x100>;
Powered by blists - more mailing lists