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Message-ID: <20240212134119.GA37175-robh@kernel.org>
Date: Mon, 12 Feb 2024 07:41:19 -0600
From: Rob Herring <robh@...nel.org>
To: Sebastian Reichel <sre@...nel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
NXP Linux Team <linux-imx@....com>,
Dong Aisheng <aisheng.dong@....com>,
Linus Walleij <linus.walleij@...aro.org>,
Dmitry Torokhov <dmitry.torokhov@...il.com>,
Mark Brown <broonie@...nel.org>,
linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1 03/14] dt-bindings: sound: fsl,imx-asrc: convert to
YAML
On Sat, Feb 10, 2024 at 02:18:07AM +0100, Sebastian Reichel wrote:
> Convert the i.MX ASRC DT binding to YAML.
>
> Signed-off-by: Sebastian Reichel <sre@...nel.org>
> ---
> .../devicetree/bindings/sound/fsl,asrc.txt | 80 ---------
> .../bindings/sound/fsl,imx-asrc.yaml | 159 ++++++++++++++++++
> 2 files changed, 159 insertions(+), 80 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/sound/fsl,asrc.txt
> create mode 100644 Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml
> diff --git a/Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml b/Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml
> new file mode 100644
> index 000000000000..bc1607ecf345
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml
> @@ -0,0 +1,159 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/sound/fsl,imx-asrc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale Asynchronous Sample Rate Converter (ASRC) Controller
> +
> +description:
> + The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of
> + a signal associated with an input clock into a signal associated with a
> + different output clock. The driver currently works as a Front End of DPCM
> + with other Back Ends Audio controller such as ESAI, SSI and SAI. It has
> + three pairs to support three substreams within totally 10 channels.
> +
> +maintainers:
> + - Shawn Guo <shawnguo@...nel.org>
> + - Sascha Hauer <s.hauer@...gutronix.de>
> +
> +properties:
> + compatible:
> + oneOf:
> + - enum:
> + - fsl,imx35-asrc
> + - fsl,imx53-asrc
> + - fsl,imx8qm-asrc
> + - fsl,imx8qxp-asrc
> + - items:
> + - enum:
> + - fsl,imx6sx-asrc
> + - fsl,imx6ul-asrc
> + - const: fsl,imx53-asrc
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + dmas:
> + maxItems: 6
> +
> + dma-names:
> + items:
> + - const: rxa
> + - const: rxb
> + - const: rxc
> + - const: txa
> + - const: txb
> + - const: txc
> +
> + clocks:
> + maxItems: 19
> +
> + clock-names:
> + items:
> + - const: mem
> + - const: ipg
> + - const: asrck_0
> + - const: asrck_1
> + - const: asrck_2
> + - const: asrck_3
> + - const: asrck_4
> + - const: asrck_5
> + - const: asrck_6
> + - const: asrck_7
> + - const: asrck_8
> + - const: asrck_9
> + - const: asrck_a
> + - const: asrck_b
> + - const: asrck_c
> + - const: asrck_d
> + - const: asrck_e
> + - const: asrck_f
> + - const: spba
> +
> + fsl,asrc-rate:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: The mutual sample rate used by DPCM Back Ends
> +
> + fsl,asrc-width:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: The mutual sample width used by DPCM Back Ends
Constraints?
> +
> + fsl,asrc-clk-map:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Defines clock map used in driver
> + <0> - select the map for asrc0 in imx8qm/imx8qxp
> + <1> - select the map for asrc1 in imx8qm/imx8qxp
Looks like constraints.
> +
> + big-endian:
> + type: boolean
> + description:
> + If this property is absent, the little endian mode will be in use as
> + default. Otherwise, the big endian mode will be in use for all the
> + device registers.
> +
> + fsl,asrc-format:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Defines a mutual sample format used by DPCM Back Ends, which can
> + replace the fsl,asrc-width. The value is 2 (S16_LE), or 6 (S24_LE).
Looks like constraints.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - dmas
> + - dma-names
> + - clocks
> + - clock-names
> + - fsl,asrc-rate
> + - fsl,asrc-width
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - fsl,imx8qm-asrc
> + - fsl,imx8qxp-asrc
> + then:
> + required:
> + - fsl,asrc-clk-map
> + else:
> + properties:
> + fsl,asrc-clk-map: false
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/clock/imx6qdl-clock.h>
> + asrc: asrc@...4000 {
> + compatible = "fsl,imx53-asrc";
> + reg = <0x02034000 0x4000>;
> + interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
> + <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
> + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
> + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
> + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
> + <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
> + <&clks IMX6QDL_CLK_SPBA>;
> + clock-names = "mem", "ipg", "asrck_0",
> + "asrck_1", "asrck_2", "asrck_3", "asrck_4",
> + "asrck_5", "asrck_6", "asrck_7", "asrck_8",
> + "asrck_9", "asrck_a", "asrck_b", "asrck_c",
> + "asrck_d", "asrck_e", "asrck_f", "spba";
> + dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
> + <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
> + dma-names = "rxa", "rxb", "rxc",
> + "txa", "txb", "txc";
> + fsl,asrc-rate = <48000>;
> + fsl,asrc-width = <16>;
> + };
> --
> 2.43.0
>
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