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Message-ID: <8c3d8fc3-2c1e-4ece-abb1-b427a909ad39@linaro.org>
Date: Thu, 15 Feb 2024 20:02:29 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Md Sadre Alam <quic_mdalam@...cinc.com>, andersson@...nel.org,
konrad.dybcio@...aro.org, broonie@...nel.org, robh@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
miquel.raynal@...tlin.com, richard@....at, vigneshr@...com,
manivannan.sadhasivam@...aro.org, linux-arm-msm@...r.kernel.org,
linux-spi@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-mtd@...ts.infradead.org
Cc: quic_srichara@...cinc.com, quic_varada@...cinc.com
Subject: Re: [PATCH 1/5] spi: dt-bindings: add binding doc for spi-qpic-snand
On 15/02/2024 14:48, Md Sadre Alam wrote:
> Add device-tree binding documentation for QCOM QPIC-SNAND-NAND Flash
> Interface.
>
A nit, subject: drop second/last, redundant "bindings". The
"dt-bindings" prefix is already stating that these are bindings.
See also:
https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18
> Co-developed-by: Sricharan Ramabadhran <quic_srichara@...cinc.com>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@...cinc.com>
> Co-developed-by: Varadarajan Narayanan <quic_varada@...cinc.com>
> Signed-off-by: Varadarajan Narayanan <quic_varada@...cinc.com>
> Signed-off-by: Md Sadre Alam <quic_mdalam@...cinc.com>
> ---
> .../bindings/spi/qcom,spi-qpic-snand.yaml | 82 +++++++++++++++++++
> 1 file changed, 82 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
>
> diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
> new file mode 100644
> index 000000000000..fa7484ce1319
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
Filename like compatible.
> @@ -0,0 +1,82 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm QPIC NAND controller
> +
> +maintainers:
> + - Md sadre Alam <quic_mdalam@...cinc.com>
> +
Provide description which will describe hardware.
> +properties:
> + compatible:
> + enum:
> + - qcom,ipq9574-snand
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 2
> + maxItems: 3
You must document the items (could be sufficient in clock-names if the
names are obvious).
Why the clocks are flexible? This given IPQ9574 has variable clock
inputs? Please explain.
> +
> + clock-names:
> + minItems: 2
> + maxItems: 3
> +
required goes here.
> +allOf:
> + - $ref: /schemas/spi/spi-controller.yaml#
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,ipq9574-snand
> +
> + then:
> + properties:
> + dmas:
> + items:
> + - description: tx DMA channel
> + - description: rx DMA channel
> + - description: cmd DMA channel
> +
> + dma-names:
> + items:
> + - const: tx
> + - const: rx
> + - const: cmd
No clue why it is here, move it to top level.
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
> + qpic_nand: spi@...0000 {
Drop unused label
> + compatible = "qcom,ipq9574-snand";
> + reg = <0x1ac00000 0x800>;
> +
> + clocks = <&gcc GCC_QPIC_CLK>,
> + <&gcc GCC_QPIC_AHB_CLK>,
> + <&gcc GCC_QPIC_IO_MACRO_CLK>;
> + clock-names = "core", "aon", "iom";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + flash@0 {
> + compatible = "spi-nand";
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + nand-ecc-engine = <&qpic_nand>;
> + nand-ecc-strength = <4>;
> + nand-ecc-step-size = <512>;
> + };
Fix indentation.
> + };
Best regards,
Krzysztof
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