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Message-ID: <17c6b3df-2acd-45e2-8167-02c629b1e972@quicinc.com>
Date: Fri, 16 Feb 2024 21:10:28 +0530
From: Kathiravan Thirumoorthy <quic_kathirav@...cinc.com>
To: Md Sadre Alam <quic_mdalam@...cinc.com>, <andersson@...nel.org>,
<konrad.dybcio@...aro.org>, <broonie@...nel.org>, <robh@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
<miquel.raynal@...tlin.com>, <richard@....at>, <vigneshr@...com>,
<manivannan.sadhasivam@...aro.org>, <linux-arm-msm@...r.kernel.org>,
<linux-spi@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-mtd@...ts.infradead.org>
CC: <quic_srichara@...cinc.com>, <quic_varada@...cinc.com>
Subject: Re: [PATCH 4/5] arm64: dts: qcom: ipq9574: Add SPI nand support
On 2/15/2024 7:18 PM, Md Sadre Alam wrote:
> Add SPI NAND support for ipq9574 SoC.
>
> Signed-off-by: Md Sadre Alam <quic_mdalam@...cinc.com>
> ---
> .../boot/dts/qcom/ipq9574-rdp-common.dtsi | 43 +++++++++++++++++++
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 27 ++++++++++++
> 2 files changed, 70 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
> index 91e104b0f865..5b54a027fa5d 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
> @@ -139,6 +139,49 @@ gpio_leds_default: gpio-leds-default-state {
> drive-strength = <8>;
> bias-pull-up;
> };
> +
> + qpic_snand_default_state: qpic-snand-default-state {
> + clock-pins {
> + pins = "gpio5";
> + function = "qspi_clk";
> + drive-strength = <8>;
> + bias-disable;
> + };
> +
> + cs-pins {
> + pins = "gpio4";
> + function = "qspi_cs";
> + drive-strength = <8>;
> + bias-disable;
> + };
> +
> + data-pins {
> + pins = "gpio0", "gpio1", "gpio2";
As per the pinctrl driver[1], there are 4 data pins.
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pinctrl/qcom/pinctrl-ipq9574.c#n296
> + function = "qspi_data";
> + drive-strength = <8>;
> + bias-disable;
> + };
> + };
> +};
> +
> +&qpic_bam {
> + status = "okay";
> +};
> +
> +&qpic_nand {
> + pinctrl-0 = <&qpic_snand_default_state>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + flash@0 {
> + compatible = "spi-nand";
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + nand-ecc-engine = <&qpic_nand>;
> + nand-ecc-strength = <4>;
> + nand-ecc-step-size = <512>;
> + };
> };
>
> &usb_0_dwc3 {
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 7f2e5cbf3bbb..d963dd2035dd 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -319,6 +319,33 @@ tcsr: syscon@...7000 {
> reg = <0x01937000 0x21000>;
> };
>
> + qpic_bam: dma-controller@...4000 {
Nodes should be ordered by unit address in ascending order. So please
move these nodes to the right place.
> + compatible = "qcom,bam-v1.7.0";
> + reg = <0x7984000 0x1c000>;
address should be padded to 8 bytes.
> + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_QPIC_AHB_CLK>;
> + clock-names = "bam_clk";
> + #dma-cells = <1>;
> + qcom,ee = <0>;
> + status = "disabled";
> + };
> +
> + qpic_nand: spi@...0000 {
> + compatible = "qcom,ipq9574-snand";
> + reg = <0x79b0000 0x10000>;
Ditto..
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&gcc GCC_QPIC_CLK>,
> + <&gcc GCC_QPIC_AHB_CLK>,
> + <&gcc GCC_QPIC_IO_MACRO_CLK>;
Fix the alignment.
> + clock-names = "core", "aon", "iom";
> + dmas = <&qpic_bam 0>,
> + <&qpic_bam 1>,
> + <&qpic_bam 2>;
Here as well.
> + dma-names = "tx", "rx", "cmd";
> + status = "disabled";
> + };
> +
> sdhc_1: mmc@...4000 {
> compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
> reg = <0x07804000 0x1000>,
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