linux-kernel - Re: [PATCH v1 0/6] SiFive cache controller PMU drivers

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20240216-shopping-unnoticed-e73e72a0e849@wendy>
Date: Fri, 16 Feb 2024 10:05:04 +0000
From: Conor Dooley <conor.dooley@...rochip.com>
To: Samuel Holland <samuel.holland@...ive.com>
CC: Will Deacon <will@...nel.org>, Mark Rutland <mark.rutland@....com>, Eric
 Lin <eric.lin@...ive.com>, Conor Dooley <conor@...nel.org>, Palmer Dabbelt
	<palmer@...belt.com>, <devicetree@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>, Paul Walmsley <paul.walmsley@...ive.com>,
	<linux-riscv@...ts.infradead.org>, Rob Herring <robh+dt@...nel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v1 0/6] SiFive cache controller PMU drivers

On Thu, Feb 15, 2024 at 04:08:12PM -0800, Samuel Holland wrote:

> All three of these cache controllers (with PMUs) have been integrated in
> SoCs by our customers. However, as none of those SoCs have been publicly
> announced yet, I cannot include SoC-specific compatible strings in this
> version of the devicetree bindings.

And I don't want to apply any of those dt-binding patches until then.
Stuff like "sifive,perfmon-counters" seems like a property that would
go away with a device-specific compatible, at least for the ccache.

Download attachment "signature.asc" of type "application/pgp-signature" (229 bytes)