linux-kernel - Re: [PATCH v1 1/6] dt-bindings: cache: Document the sifive,perfmon-counters property

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Message-ID: <eeb2331d-10e6-4902-91ba-85896a8f0ee1@linaro.org>
Date: Sat, 17 Feb 2024 10:00:41 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Samuel Holland <samuel.holland@...ive.com>, Will Deacon
 <will@...nel.org>, Mark Rutland <mark.rutland@....com>,
 Eric Lin <eric.lin@...ive.com>, Conor Dooley <conor@...nel.org>
Cc: Palmer Dabbelt <palmer@...belt.com>, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, Paul Walmsley <paul.walmsley@...ive.com>,
 linux-riscv@...ts.infradead.org, Rob Herring <robh+dt@...nel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
 linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v1 1/6] dt-bindings: cache: Document the
 sifive,perfmon-counters property

On 16/02/2024 01:08, Samuel Holland wrote:
> The SiFive Composable Cache controller contains an optional PMU with a
> configurable number of event counters. Document a property which

Configurable in what context? By chip designers or by OS? Why this
cannot be deduced from the compatible?

> describes the number of available counters.
> 
> Signed-off-by: Samuel Holland <samuel.holland@...ive.com>
> ---
> 
>  Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
>  

Best regards,
Krzysztof