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Message-ID: <f84a4933-ce7a-4820-9b57-84a1549602ff@linaro.org>
Date: Sat, 17 Feb 2024 15:27:38 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Markus Schneider-Pargmann <msp@...libre.com>,
Viresh Kumar <vireshk@...nel.org>, Nishanth Menon <nm@...com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>, Vignesh Raghavendra <vigneshr@...com>,
Tero Kristo <kristo@...nel.org>, "Rafael J . Wysocki" <rafael@...nel.org>
Cc: Andrew Davis <afd@...com>, Dhruva Gole <d-gole@...com>,
linux-pm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 1/3] dt-bindings: cpufreq: Add nvmem-cells for chip
information
On 06/02/2024 15:57, Markus Schneider-Pargmann wrote:
> Add nvmem-cells to describe chip information like chipvariant and
> chipspeed. If nvmem-cells are used, the syscon property is not necessary
> anymore.
>
> Signed-off-by: Markus Schneider-Pargmann <msp@...libre.com>
> Acked-by: Andrew Davis <afd@...com>
> ---
> .../bindings/opp/operating-points-v2-ti-cpu.yaml | 16 +++++++++++++++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml b/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml
> index 02d1d2c17129..b1881a0834fe 100644
> --- a/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml
> +++ b/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml
> @@ -34,6 +34,14 @@ properties:
> points to syscon node representing the control module
> register space of the SoC.
>
> + nvmem-cells:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
Why redefining the type?
Best regards,
Krzysztof
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