linux-kernel - Re: [PATCH] drivers/iommu: Ensure that the queue base address is successfully written during SMMU initialization.

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Message-ID: <CAE2F3rA1Lb_ayrLQTw+urtNSMoBg9q6CmcSsP7_dZwbfiYygsw@mail.gmail.com>
Date: Sun, 18 Feb 2024 21:44:47 -0800
From: Daniel Mentz <danielmentz@...gle.com>
To: "ni.liqiang" <niliqiang.io@...il.com>
Cc: Will Deacon <will@...nel.org>, Robin Murphy <robin.murphy@....com>, 
	Joerg Roedel <joro@...tes.org>, "jin . qi" <jin.qi@....com.cn>, 
	linux-arm-kernel@...ts.infradead.org, iommu@...ts.linux.dev, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] drivers/iommu: Ensure that the queue base address is
 successfully written during SMMU initialization.

On Sat, Feb 17, 2024 at 9:02 PM ni.liqiang <niliqiang.io@...il.com> wrote:
> If there are no memory barriers, how can we ensure this order?

 The SMMU registers are accessed using Device-nGnRE attributes. It is
my understanding that, for Device-nGnRE, the Arm architecture requires
that writes to the same peripheral arrive at the endpoint in program
order.