linux-kernel - Re: [PATCH] drivers/iommu: Ensure that the queue base address is successfully written during SMMU initialization.

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Message-ID: <20240219091709.GA4105@willie-the-truck>
Date: Mon, 19 Feb 2024 09:17:09 +0000
From: Will Deacon <will@...nel.org>
To: Daniel Mentz <danielmentz@...gle.com>
Cc: "ni.liqiang" <niliqiang.io@...il.com>,
	Robin Murphy <robin.murphy@....com>, Joerg Roedel <joro@...tes.org>,
	"jin . qi" <jin.qi@....com.cn>,
	linux-arm-kernel@...ts.infradead.org, iommu@...ts.linux.dev,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] drivers/iommu: Ensure that the queue base address is
 successfully written during SMMU initialization.

On Sun, Feb 18, 2024 at 09:44:47PM -0800, Daniel Mentz wrote:
> On Sat, Feb 17, 2024 at 9:02 PM ni.liqiang <niliqiang.io@...il.com> wrote:
> > If there are no memory barriers, how can we ensure this order?
> 
>  The SMMU registers are accessed using Device-nGnRE attributes. It is
> my understanding that, for Device-nGnRE, the Arm architecture requires
> that writes to the same peripheral arrive at the endpoint in program
> order.

Yup, that's correct. The "nR" part means "non-Reordering", so something
else is going on here.

Will