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Message-ID: <CAK9=C2Umyc5KpZSQiAVxRA8NNqj3yuvqX4d8pMnc21jQjwZkWg@mail.gmail.com>
Date: Tue, 20 Feb 2024 22:09:46 +0530
From: Anup Patel <apatel@...tanamicro.com>
To: Björn Töpel <bjorn@...nel.org>
Cc: Palmer Dabbelt <palmer@...belt.com>, Paul Walmsley <paul.walmsley@...ive.com>,
Thomas Gleixner <tglx@...utronix.de>, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Frank Rowand <frowand.list@...il.com>,
Conor Dooley <conor+dt@...nel.org>, devicetree@...r.kernel.org,
Saravana Kannan <saravanak@...gle.com>, Marc Zyngier <maz@...nel.org>, Anup Patel <anup@...infault.org>,
linux-kernel@...r.kernel.org, Atish Patra <atishp@...shpatra.org>,
linux-riscv@...ts.infradead.org, linux-arm-kernel@...ts.infradead.org,
Andrew Jones <ajones@...tanamicro.com>
Subject: Re: [PATCH v13 07/13] irqchip/riscv-imsic: Add device MSI domain
support for platform devices
On Tue, Feb 20, 2024 at 5:23 PM Björn Töpel <bjorn@...nelorg> wrote:
>
> Anup Patel <apatel@...tanamicro.com> writes:
>
> > The Linux platform MSI support allows per-device MSI domains so let
> > us add a platform irqchip driver for RISC-V IMSIC which provides a
> > base IRQ domain with MSI parent support for platform device domains.
> >
> > This driver assumes that the IMSIC state is already initialized by
> > the IMSIC early driver.
> >
> > Signed-off-by: Anup Patel <apatel@...tanamicro.com>
> > ---
> > drivers/irqchip/Makefile | 2 +-
> > drivers/irqchip/irq-riscv-imsic-platform.c | 346 +++++++++++++++++++++
> > drivers/irqchip/irq-riscv-imsic-state.h | 1 +
> > 3 files changed, 348 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/irqchip/irq-riscv-imsic-platform.c
> >
> > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> > index d714724387ce..abca445a3229 100644
> > --- a/drivers/irqchip/Makefile
> > +++ b/drivers/irqchip/Makefile
> > @@ -95,7 +95,7 @@ obj-$(CONFIG_QCOM_MPM) += irq-qcom-mpm.o
> > obj-$(CONFIG_CSKY_MPINTC) += irq-csky-mpintc.o
> > obj-$(CONFIG_CSKY_APB_INTC) += irq-csky-apb-intc.o
> > obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o
> > -obj-$(CONFIG_RISCV_IMSIC) += irq-riscv-imsic-state.o irq-riscv-imsic-early.o
> > +obj-$(CONFIG_RISCV_IMSIC) += irq-riscv-imsic-state.o irq-riscv-imsic-early.o irq-riscv-imsic-platform.o
> > obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o
> > obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o
> > obj-$(CONFIG_IMX_INTMUX) += irq-imx-intmux.o
> > diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/irq-riscv-imsic-platform.c
> > new file mode 100644
> > index 000000000000..7ee44c493dbc
> > --- /dev/null
> > +++ b/drivers/irqchip/irq-riscv-imsic-platform.c
> > @@ -0,0 +1,346 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2021 Western Digital Corporation or its affiliates.
> > + * Copyright (C) 2022 Ventana Micro Systems Inc.
> > + */
> > +
> > +#define pr_fmt(fmt) "riscv-imsic: " fmt
> > +#include <linux/bitmap.h>
> > +#include <linux/cpu.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/io.h>
> > +#include <linux/irq.h>
> > +#include <linux/irqchip.h>
> > +#include <linux/irqdomain.h>
> > +#include <linux/module.h>
> > +#include <linux/msi.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/spinlock.h>
> > +#include <linux/smp.h>
> > +
> > +#include "irq-riscv-imsic-state.h"
> > +
> > +static bool imsic_cpu_page_phys(unsigned int cpu, unsigned int guest_index,
> > + phys_addr_t *out_msi_pa)
> > +{
> > + struct imsic_global_config *global;
> > + struct imsic_local_config *local;
> > +
> > + global = &imsic->global;
> > + local = per_cpu_ptr(global->local, cpu);
> > +
> > + if (BIT(global->guest_index_bits) <= guest_index)
> > + return false;
> > +
> > + if (out_msi_pa)
> > + *out_msi_pa = local->msi_pa +
> > + (guest_index * IMSIC_MMIO_PAGE_SZ);
> > +
> > + return true;
> > +}
> > +
> > +static void imsic_irq_mask(struct irq_data *d)
> > +{
> > + imsic_vector_mask(irq_data_get_irq_chip_data(d));
> > +}
> > +
> > +static void imsic_irq_unmask(struct irq_data *d)
> > +{
> > + imsic_vector_unmask(irq_data_get_irq_chip_data(d));
> > +}
> > +
> > +static int imsic_irq_retrigger(struct irq_data *d)
> > +{
> > + struct imsic_vector *vec = irq_data_get_irq_chip_data(d);
> > + struct imsic_local_config *local;
> > +
> > + if (WARN_ON(vec == NULL))
>
> Checkpatch: use !vec
Okay, I will update.
>
> > + return -ENOENT;
> > +
> > + local = per_cpu_ptr(imsic->global.local, vec->cpu);
> > + writel_relaxed(vec->local_id, local->msi_va);
> > + return 0;
> > +}
> > +
> > +static void imsic_irq_compose_vector_msg(struct imsic_vector *vec, struct msi_msg *msg)
> > +{
> > + phys_addr_t msi_addr;
> > +
> > + if (WARN_ON(vec == NULL))
>
> Checkpatch: use !vec
Okay, I will update.
>
> > + return;
> > +
> > + if (WARN_ON(!imsic_cpu_page_phys(vec->cpu, 0, &msi_addr)))
> > + return;
> > +
> > + msg->address_hi = upper_32_bits(msi_addr);
> > + msg->address_lo = lower_32_bits(msi_addr);
> > + msg->data = vec->local_id;
> > +}
> > +
> > +static void imsic_irq_compose_msg(struct irq_data *d, struct msi_msg *msg)
> > +{
> > + imsic_irq_compose_vector_msg(irq_data_get_irq_chip_data(d), msg);
> > +}
> > +
> > +#ifdef CONFIG_SMP
> > +static void imsic_msi_update_msg(struct irq_data *d, struct imsic_vector *vec)
> > +{
> > + struct msi_msg msg[2] = { [1] = { }, };
> > +
> > + imsic_irq_compose_vector_msg(vec, msg);
> > + irq_data_get_irq_chip(d)->irq_write_msi_msg(d, msg);
> > +}
> > +
> > +static int imsic_irq_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
> > + bool force)
> > +{
> > + struct imsic_vector *old_vec, *new_vec;
> > + struct irq_data *pd = d->parent_data;
> > +
> > + old_vec = irq_data_get_irq_chip_data(pd);
> > + if (WARN_ON(old_vec == NULL))
>
> Checkpatch: use !old_vec
Okay, I will update.
>
> > + return -ENOENT;
> > +
> > + /* If old vector cpu belongs to the target cpumask then do nothing */
> > + if (cpumask_test_cpu(old_vec->cpu, mask_val))
> > + return IRQ_SET_MASK_OK_DONE;
> > +
> > + /* If move is already in-flight then return failure */
> > + if (imsic_vector_get_move(old_vec))
> > + return -EBUSY;
> > +
> > + /* Get a new vector on the desired set of CPUs */
> > + new_vec = imsic_vector_alloc(old_vec->hwirq, mask_val);
> > + if (!new_vec)
> > + return -ENOSPC;
> > +
> > + /* Point device to the new vector */
> > + imsic_msi_update_msg(d, new_vec);
> > +
> > + /* Update irq descriptors with the new vector */
> > + pd->chip_data = new_vec;
> > +
> > + /* Update effective affinity of parent irq data */
> > + irq_data_update_effective_affinity(pd, cpumask_of(new_vec->cpu));
> > +
> > + /* Move state of the old vector to the new vector */
> > + imsic_vector_move(old_vec, new_vec);
> > +
> > + return IRQ_SET_MASK_OK_DONE;
> > +}
> > +#endif
> > +
> > +static struct irq_chip imsic_irq_base_chip = {
> > + .name = "IMSIC",
> > + .irq_mask = imsic_irq_mask,
> > + .irq_unmask = imsic_irq_unmask,
> > + .irq_retrigger = imsic_irq_retrigger,
> > + .irq_compose_msi_msg = imsic_irq_compose_msg,
> > + .flags = IRQCHIP_SKIP_SET_WAKE |
> > + IRQCHIP_MASK_ON_SUSPEND,
> > +};
> > +
> > +static int imsic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
> > + unsigned int nr_irqs, void *args)
> > +{
> > + struct imsic_vector *vec;
> > +
> > + /* Legacy-MSI or multi-MSI not supported yet. */
> > + if (nr_irqs > 1)
> > + return -ENOTSUPP;
>
> Checkpatch: WARNING: ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP
Okay, I will update.
Regards,
Anup
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