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Message-ID: <0dae7231-6bd1-b7fc-4a5e-b0787b0adaba@quicinc.com>
Date: Tue, 20 Feb 2024 17:36:39 +0530
From: Md Sadre Alam <quic_mdalam@...cinc.com>
To: Conor Dooley <conor@...nel.org>
CC: <andersson@...nel.org>, <konrad.dybcio@...aro.org>, <broonie@...nel.org>,
<robh@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
<conor+dt@...nel.org>, <miquel.raynal@...tlin.com>, <richard@....at>,
<vigneshr@...com>, <manivannan.sadhasivam@...aro.org>,
<linux-arm-msm@...r.kernel.org>, <linux-spi@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-mtd@...ts.infradead.org>, <quic_srichara@...cinc.com>,
<quic_varada@...cinc.com>
Subject: Re: [PATCH 1/5] spi: dt-bindings: add binding doc for spi-qpic-snand
On 2/15/2024 7:54 PM, Conor Dooley wrote:
> On Thu, Feb 15, 2024 at 07:18:52PM +0530, Md Sadre Alam wrote:
>> Add device-tree binding documentation for QCOM QPIC-SNAND-NAND Flash
>> Interface.
>>
>> Co-developed-by: Sricharan Ramabadhran <quic_srichara@...cinc.com>
>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@...cinc.com>
>> Co-developed-by: Varadarajan Narayanan <quic_varada@...cinc.com>
>> Signed-off-by: Varadarajan Narayanan <quic_varada@...cinc.com>
>> Signed-off-by: Md Sadre Alam <quic_mdalam@...cinc.com>
>> ---
>> .../bindings/spi/qcom,spi-qpic-snand.yaml | 82 +++++++++++++++++++
>> 1 file changed, 82 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
>> new file mode 100644
>> index 000000000000..fa7484ce1319
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
>> @@ -0,0 +1,82 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm QPIC NAND controller
>> +
>> +maintainers:
>> + - Md sadre Alam <quic_mdalam@...cinc.com>
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - qcom,ipq9574-snand
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + minItems: 2
>> + maxItems: 3
>> +
>> + clock-names:
>> + minItems: 2
>> + maxItems: 3
>> +
>> +allOf:
>> + - $ref: /schemas/spi/spi-controller.yaml#
>> + - if:
>
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - qcom,ipq9574-snand
>> +
>> + then:
>> + properties:
>> + dmas:
>> + items:
>> + - description: tx DMA channel
>> + - description: rx DMA channel
>> + - description: cmd DMA channel
>> +
>> + dma-names:
>> + items:
>> + - const: tx
>> + - const: rx
>> + - const: cmd
>
> None of this complexity here is needed, you have only one device in this
> binding and therefore can define these properties at the top level.
Thanks for reviewing, Will fix this in next patch.
>
> Cheers,
> Conor.
>
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
>> + qpic_nand: spi@...0000 {
>> + compatible = "qcom,ipq9574-snand";
>> + reg = <0x1ac00000 0x800>;
>> +
>> + clocks = <&gcc GCC_QPIC_CLK>,
>> + <&gcc GCC_QPIC_AHB_CLK>,
>> + <&gcc GCC_QPIC_IO_MACRO_CLK>;
>> + clock-names = "core", "aon", "iom";
>> +
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + flash@0 {
>> + compatible = "spi-nand";
>> + reg = <0>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + nand-ecc-engine = <&qpic_nand>;
>> + nand-ecc-strength = <4>;
>> + nand-ecc-step-size = <512>;
>> + };
>> + };
>> --
>> 2.34.1
>>
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