linux-kernel - Re: [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller

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Date: Thu, 22 Feb 2024 22:36:47 +0100
From: Thomas Gleixner <tglx@...utronix.de>
To: Yu Chien Peter Lin <peterlin@...estech.com>, acme@...nel.org,
 adrian.hunter@...el.com, ajones@...tanamicro.com,
 alexander.shishkin@...ux.intel.com, andre.przywara@....com,
 anup@...infault.org, aou@...s.berkeley.edu, atishp@...shpatra.org,
 conor+dt@...nel.org, conor.dooley@...rochip.com, conor@...nel.org,
 devicetree@...r.kernel.org, evan@...osinc.com, geert+renesas@...der.be,
 guoren@...nel.org, heiko@...ech.de, irogers@...gle.com,
 jernej.skrabec@...il.com, jolsa@...nel.org, jszhang@...nel.org,
 krzysztof.kozlowski+dt@...aro.org, linux-arm-kernel@...ts.infradead.org,
 linux-kernel@...r.kernel.org, linux-perf-users@...r.kernel.org,
 linux-renesas-soc@...r.kernel.org, linux-riscv@...ts.infradead.org,
 linux-sunxi@...ts.linux.dev, locus84@...estech.com, magnus.damm@...il.com,
 mark.rutland@....com, mingo@...hat.com, n.shubin@...ro.com,
 namhyung@...nel.org, palmer@...belt.com, paul.walmsley@...ive.com,
 peterlin@...estech.com, peterz@...radead.org,
 prabhakar.mahadev-lad.rj@...renesas.com, rdunlap@...radead.org,
 robh+dt@...nel.org, samuel@...lland.org, sunilvl@...tanamicro.com,
 tim609@...estech.com, uwu@...nowy.me, wens@...e.org, will@...nel.org,
 inochiama@...look.com, unicorn_wang@...look.com, wefu@...hat.com
Cc: Randolph <randolph@...estech.com>
Subject: Re: [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level
 interrupt controller

On Thu, Feb 22 2024 at 16:39, Yu Chien Peter Lin wrote:
> Add support for the Andes hart-level interrupt controller. This
> controller provides interrupt mask/unmask functions to access the
> custom register (SLIE) where the non-standard S-mode local interrupt
> enable bits are located. The base of custom interrupt number is set
> to 256.
>
> To share the riscv_intc_domain_map() with the generic RISC-V INTC and
> ACPI, add a chip parameter to riscv_intc_init_common(), so it can be
> passed to the irq_domain_set_info() as a private data.
>
> Andes hart-level interrupt controller requires the "andestech,cpu-intc"
> compatible string to be present in interrupt-controller of cpu node to
> enable the use of custom local interrupt source.
> e.g.,
>
>   cpu0: cpu@0 {
>       compatible = "andestech,ax45mp", "riscv";
>       ...
>       cpu0-intc: interrupt-controller {
>           #interrupt-cells = <0x01>;
>           compatible = "andestech,cpu-intc", "riscv,cpu-intc";
>           interrupt-controller;
>       };
>   };
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@...estech.com>
> Reviewed-by: Randolph <randolph@...estech.com>
> Reviewed-by: Anup Patel <anup@...infault.org>

Reviewed-by: Thomas Gleixner <tglx@...utronix.de>

Palmer, feel free to take this through the riscv tree. I have no other
changes pending against that driver.

Thanks,

        tglx