linux-kernel - Re: [PATCH v3 4/4] riscv: dts: add resets property for uart node

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Message-ID:
 <IA1PR20MB495398760802EC53FF4F7EEFBB562@IA1PR20MB4953.namprd20.prod.outlook.com>
Date: Thu, 22 Feb 2024 08:35:14 +0800
From: Inochi Amaoto <inochiama@...look.com>
To: Chen Wang <unicornxw@...il.com>, aou@...s.berkeley.edu, 
	chao.wei@...hgo.com, conor@...nel.org, krzysztof.kozlowski+dt@...aro.org, 
	palmer@...belt.com, paul.walmsley@...ive.com, p.zabel@...gutronix.de, 
	robh+dt@...nel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	linux-riscv@...ts.infradead.org, haijiao.liu@...hgo.com, xiaoguang.xing@...hgo.com, 
	guoren@...nel.org, jszhang@...nel.org
Cc: Chen Wang <unicorn_wang@...look.com>, 
	Inochi Amaoto <inochiama@...look.com>
Subject: Re: [PATCH v3 4/4] riscv: dts: add resets property for uart node

LGTM

Reviewed-by: Inochi Amaoto <inochiama@...look.com>

On Tue, Jan 30, 2024 at 09:50:51AM +0800, Chen Wang wrote:
> From: Chen Wang <unicorn_wang@...look.com>
> 
> Add resets property for uart0 for completeness, although it is
> deasserted by default.
> 
> Signed-off-by: Chen Wang <unicorn_wang@...look.com>
> ---
>  arch/riscv/boot/dts/sophgo/sg2042.dtsi | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> index eeb341e16bfd..81fda312f988 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> @@ -343,6 +343,7 @@ uart0: serial@...0000000 {
>  			clock-frequency = <500000000>;
>  			reg-shift = <2>;
>  			reg-io-width = <4>;
> +			resets = <&rstgen RST_UART0>;
>  			status = "disabled";
>  		};
>  	};
> -- 
> 2.25.1
>