linux-kernel - Re: [PATCH v7 7/7] PCI: qcom: Add OPP support to scale performance state of power domain

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date: Tue, 27 Feb 2024 17:36:36 -0600
From: Bjorn Helgaas <helgaas@...nel.org>
To: Krishna chaitanya chundru <quic_krichai@...cinc.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
	Konrad Dybcio <konrad.dybcio@...aro.org>,
	Lorenzo Pieralisi <lpieralisi@...nel.org>,
	Krzysztof Wilczyński <kw@...ux.com>,
	Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
	Rob Herring <robh+dt@...nel.org>,
	Johan Hovold <johan+linaro@...nel.org>,
	Brian Masney <bmasney@...hat.com>,
	Georgi Djakov <djakov@...nel.org>, linux-arm-msm@...r.kernel.org,
	linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, vireshk@...nel.org,
	quic_vbadigan@...cinc.com, quic_skananth@...cinc.com,
	quic_nitegupt@...cinc.com, quic_parass@...cinc.com
Subject: Re: [PATCH v7 7/7] PCI: qcom: Add OPP support to scale performance
 state of power domain

On Fri, Feb 23, 2024 at 08:18:04PM +0530, Krishna chaitanya chundru wrote:
> QCOM Resource Power Manager-hardened (RPMh) is a hardware block which
> maintains hardware state of a regulator by performing max aggregation of
> the requests made by all of the clients.
> 
> PCIe controller can operate on different RPMh performance state of power
> domain based up on the speed of the link. And this performance state varies
> from target to target.

s/up on/on/ (or "upon" if you prefer) (also below)

I understand changing the performance state based on the link speed,
but I don't understand the variation from target to target.  Do you
mean just that the link speed may vary based on the rates supported by
the downstream device?

> It is manadate to scale the performance state based up on the PCIe speed
> link operates so that SoC can run under optimum power conditions.

It sounds like it's more power efficient, but not actually
*mandatory*.  Maybe something like this?

  The SoC can be more power efficient if we scale the performance
  state based on the aggregate PCIe link speed.

> Add Operating Performance Points(OPP) support to vote for RPMh state based
> upon the speed link is operating.

Space before open paren, e.g., "Points (OPP)".

"... based on the link speed."

> OPP can handle ICC bw voting also, so move ICC bw voting through OPP
> framework if OPP entries are present.
> 
> In PCIe certain speeds like GEN1x2 & GEN2x1 or GEN3x2 & GEN4x1 use
> same bw and frequency and thus the OPP entry, so use frequency based
> search to reduce number of entries in the OPP table.

GEN1x2, GEN2x1, etc are not "speeds".  I would say:

  Different link configurations may share the same aggregate speed,
  e.g., a 2.5 GT/s x2 link and a 5.0 GT/s x1 link have the same speed
  and share the same OPP entry.

> Don't initialize ICC if OPP is supported.

Because?  Maybe this should say something about OPP including the ICC
voting?

> +		ret = icc_set_bw(pcie->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed));

Wrap to fit in 80 columns.

> +	 * Use highest OPP here if the OPP table is present. At the end of the probe(),
> +	 * OPP will be updated using qcom_pcie_icc_opp_update().

Wrap to fit in 80 columns.

> +	/* Skip ICC init if OPP is supported as ICC bw vote is handled by OPP framework */

Wrap to fit in 80 columns.